1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  *  Surface RT SPL stage configuration
4  *
5  *  (C) Copyright 2010-2013
6  *  NVIDIA Corporation <www.nvidia.com>
7  *
8  *  (C) Copyright 2021
9  *  Svyatoslav Ryhel <clamor95@gmail.com>
10  */
11 
12 #include <asm/arch/tegra.h>
13 #include <asm/arch-tegra/tegra_i2c.h>
14 #include <linux/delay.h>
15 
16 #define TPS65911_I2C_ADDR		(0x2D << 1)
17 #define TPS65911_VDDCTRL_OP_REG		0x28
18 #define TPS65911_VDDCTRL_SR_REG		0x27
19 #define TPS65911_VDDCTRL_OP_DATA	(0x2400 | TPS65911_VDDCTRL_OP_REG)
20 #define TPS65911_VDDCTRL_SR_DATA	(0x0100 | TPS65911_VDDCTRL_SR_REG)
21 
22 #define TPS62361B_I2C_ADDR		(0x60 << 1)
23 #define TPS62361B_SET3_REG		0x03
24 #define TPS62361B_SET3_DATA		(0x4600 | TPS62361B_SET3_REG)
25 
pmic_enable_cpu_vdd(void)26 void pmic_enable_cpu_vdd(void)
27 {
28 	/* Set VDD_CORE to 1.200V. */
29 	tegra_i2c_ll_write(TPS62361B_I2C_ADDR, TPS62361B_SET3_DATA);
30 
31 	udelay(1000);
32 
33 	/*
34 	 * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.
35 	 * First set VDD to 1.0125V, then enable the VDD regulator.
36 	 */
37 	tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_OP_DATA);
38 	udelay(1000);
39 	tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_SR_DATA);
40 	udelay(10 * 1000);
41 }
42