1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Copyright (C) 2024 PHYTEC Messtechnik GmbH
4 * Author: Wadim Egorov <w.egorov@phytec.de>
5 */
6
7 #include "k3_ddrss_patch.h"
8
9 #include <fdt_support.h>
10 #include <linux/errno.h>
11
12 #ifdef CONFIG_K3_AM64_DDRSS
13 #define LPDDR4_INTR_CTL_REG_COUNT (423U)
14 #define LPDDR4_INTR_PHY_INDEP_REG_COUNT (345U)
15 #define LPDDR4_INTR_PHY_REG_COUNT (1406U)
16 #endif
17
fdt_setprop_inplace_idx_u32(void * fdt,int nodeoffset,const char * name,uint32_t idx,u32 val)18 static int fdt_setprop_inplace_idx_u32(void *fdt, int nodeoffset,
19 const char *name, uint32_t idx, u32 val)
20 {
21 val = cpu_to_be32(val);
22 return fdt_setprop_inplace_namelen_partial(fdt, nodeoffset, name,
23 strlen(name),
24 idx * sizeof(val), &val,
25 sizeof(val));
26 }
27
fdt_apply_ddrss_timings_patch(void * fdt,struct ddrss * ddrss)28 int fdt_apply_ddrss_timings_patch(void *fdt, struct ddrss *ddrss)
29 {
30 int i, j;
31 int ret;
32 int mem_offset;
33
34 mem_offset = fdt_path_offset(fdt, "/memorycontroller@f300000");
35 if (mem_offset < 0)
36 return -ENODEV;
37
38 for (i = 0; i < LPDDR4_INTR_CTL_REG_COUNT; i++)
39 for (j = 0; j < ddrss->ctl_regs_num; j++)
40 if (i == ddrss->ctl_regs[j].off) {
41 ret = fdt_setprop_inplace_idx_u32(fdt,
42 mem_offset, "ti,ctl-data", i,
43 ddrss->ctl_regs[j].val);
44 if (ret)
45 return ret;
46 }
47
48 for (i = 0; i < LPDDR4_INTR_PHY_INDEP_REG_COUNT; i++)
49 for (j = 0; j < ddrss->pi_regs_num; j++)
50 if (i == ddrss->pi_regs[j].off) {
51 ret = fdt_setprop_inplace_idx_u32(fdt,
52 mem_offset, "ti,pi-data", i,
53 ddrss->pi_regs[j].val);
54 if (ret)
55 return ret;
56 }
57
58 for (i = 0; i < LPDDR4_INTR_PHY_REG_COUNT; i++)
59 for (j = 0; j < ddrss->phy_regs_num; j++)
60 if (i == ddrss->phy_regs[j].off) {
61 ret = fdt_setprop_inplace_idx_u32(fdt,
62 mem_offset, "ti,phy-data", i,
63 ddrss->phy_regs[j].val);
64 if (ret)
65 return ret;
66 }
67
68 return 0;
69 }
70