1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (C) 2020 PHYTEC Messtechnik GmbH
4 * Author: Teresa Remmet <t.remmet@phytec.de>
5 */
6
7 #include <asm/arch/clock.h>
8 #include <asm/arch/ddr.h>
9 #include <asm/arch/imx8mp_pins.h>
10 #include <asm/arch/sys_proto.h>
11 #include <asm/global_data.h>
12 #include <asm/mach-imx/boot_mode.h>
13 #include <asm/mach-imx/gpio.h>
14 #include <asm/mach-imx/mxc_i2c.h>
15 #include <asm/mach-imx/iomux-v3.h>
16 #include <hang.h>
17 #include <init.h>
18 #include <log.h>
19 #include <power/pmic.h>
20 #include <power/pca9450.h>
21 #include <spl.h>
22
23 #include "lpddr4_timing.h"
24 #include "../common/imx8m_som_detection.h"
25
26 DECLARE_GLOBAL_DATA_PTR;
27
28 #define EEPROM_ADDR 0x51
29 #define EEPROM_ADDR_FALLBACK 0x59
30
spl_board_boot_device(enum boot_device boot_dev_spl)31 int spl_board_boot_device(enum boot_device boot_dev_spl)
32 {
33 return BOOT_DEVICE_BOOTROM;
34 }
35
36 enum phytec_imx8mp_ddr_eeprom_code {
37 PHYTEC_IMX8MP_DDR_1GB = 2,
38 PHYTEC_IMX8MP_DDR_2GB = 3,
39 PHYTEC_IMX8MP_DDR_4GB = 5,
40 PHYTEC_IMX8MP_DDR_8GB = 7,
41 PHYTEC_IMX8MP_DDR_4GB_2GHZ = 8,
42 };
43
spl_dram_init(void)44 void spl_dram_init(void)
45 {
46 int ret;
47 bool use_2ghz_timings = false;
48 enum phytec_imx8mp_ddr_eeprom_code size = PHYTEC_EEPROM_INVAL;
49
50 ret = phytec_eeprom_data_setup_fallback(NULL, 0, EEPROM_ADDR,
51 EEPROM_ADDR_FALLBACK);
52 if (ret && !IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_FIX))
53 goto out;
54
55 ret = phytec_imx8m_detect(NULL);
56 if (!ret)
57 phytec_print_som_info(NULL);
58
59 if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_FIX)) {
60 if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_1GB))
61 size = PHYTEC_IMX8MP_DDR_1GB;
62 else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_2GB))
63 size = PHYTEC_IMX8MP_DDR_2GB;
64 else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_4GB))
65 size = PHYTEC_IMX8MP_DDR_4GB;
66 else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_8GB))
67 size = PHYTEC_IMX8MP_DDR_8GB;
68 } else {
69 size = phytec_get_imx8m_ddr_size(NULL);
70 }
71
72 if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_FREQ_FIX)) {
73 if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_USE_2GHZ_RAM_TIMINGS)) {
74 if (size == PHYTEC_IMX8MP_DDR_4GB)
75 size = PHYTEC_IMX8MP_DDR_4GB_2GHZ;
76 else
77 use_2ghz_timings = true;
78 } else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_USE_1_5GHZ_RAM_TIMINGS)) {
79 if (size == PHYTEC_IMX8MP_DDR_4GB_2GHZ)
80 size = PHYTEC_IMX8MP_DDR_4GB;
81 else
82 use_2ghz_timings = false;
83 }
84 } else {
85 u8 rev = phytec_get_rev(NULL);
86 u8 somtype = phytec_get_som_type(NULL);
87
88 if (rev != PHYTEC_EEPROM_INVAL &&
89 (rev >= 3 || (somtype == SOM_TYPE_PCL && rev >= 1)))
90 use_2ghz_timings = true;
91 }
92
93 switch (size) {
94 case PHYTEC_IMX8MP_DDR_1GB:
95 if (use_2ghz_timings)
96 set_dram_timings_2ghz_1gb();
97 else
98 set_dram_timings_1_5ghz_1gb();
99 break;
100 case PHYTEC_IMX8MP_DDR_2GB:
101 if (use_2ghz_timings)
102 set_dram_timings_2ghz_2gb();
103 break;
104 case PHYTEC_IMX8MP_DDR_4GB:
105 set_dram_timings_1_5ghz_4gb();
106 break;
107 case PHYTEC_IMX8MP_DDR_4GB_2GHZ:
108 set_dram_timings_2ghz_4gb();
109 break;
110 case PHYTEC_IMX8MP_DDR_8GB:
111 set_dram_timings_2ghz_8gb();
112 break;
113 default:
114 goto out;
115 }
116 ddr_init(&dram_timing);
117 return;
118 out:
119 printf("Could not detect correct RAM size. Fallback to default.\n");
120 ddr_init(&dram_timing);
121 }
122
123 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
124 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
125 struct i2c_pads_info i2c_pad_info1 = {
126 .scl = {
127 .i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC,
128 .gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC,
129 .gp = IMX_GPIO_NR(5, 14),
130 },
131 .sda = {
132 .i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC,
133 .gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC,
134 .gp = IMX_GPIO_NR(5, 15),
135 },
136 };
137
power_init_board(void)138 int power_init_board(void)
139 {
140 struct pmic *p;
141 int ret;
142
143 ret = power_pca9450_init(0, 0x25);
144 if (ret)
145 printf("power init failed");
146 p = pmic_get("PCA9450");
147 pmic_probe(p);
148
149 /* BUCKxOUT_DVS0/1 control BUCK123 output */
150 pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
151
152 /* Increase VDD_SOC and VDD_ARM to OD voltage 0.95V */
153 pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C);
154 pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C);
155
156 /* Set BUCK1 DVS1 to suspend controlled through PMIC_STBY_REQ */
157 pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14);
158 pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
159
160 /* Set WDOG_B_CFG to cold reset */
161 pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1);
162
163 return 0;
164 }
165
spl_board_init(void)166 void spl_board_init(void)
167 {
168 arch_misc_init();
169
170 /* Set GIC clock to 500Mhz for OD VDD_SOC. */
171 clock_enable(CCGR_GIC, 0);
172 clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
173 clock_enable(CCGR_GIC, 1);
174 }
175
board_fit_config_name_match(const char * name)176 int board_fit_config_name_match(const char *name)
177 {
178 return 0;
179 }
180
board_init_f(ulong dummy)181 void board_init_f(ulong dummy)
182 {
183 int ret;
184
185 arch_cpu_init();
186
187 init_uart_clk(0);
188
189 ret = spl_early_init();
190 if (ret) {
191 debug("spl_early_init() failed: %d\n", ret);
192 hang();
193 }
194
195 preloader_console_init();
196
197 enable_tzc380();
198
199 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
200
201 power_init_board();
202
203 /* DDR initialization */
204 spl_dram_init();
205 }
206