1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * board/renesas/lager/lager.c
4 * This file is lager board support.
5 *
6 * Copyright (C) 2013 Renesas Electronics Corporation
7 * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
8 */
9
10 #include <clock_legacy.h>
11 #include <cpu_func.h>
12 #include <env.h>
13 #include <env_internal.h>
14 #include <hang.h>
15 #include <init.h>
16 #include <malloc.h>
17 #include <netdev.h>
18 #include <dm.h>
19 #include <asm/global_data.h>
20 #include <dm/platform_data/serial_sh.h>
21 #include <asm/processor.h>
22 #include <asm/mach-types.h>
23 #include <asm/io.h>
24 #include <linux/bitops.h>
25 #include <linux/delay.h>
26 #include <linux/errno.h>
27 #include <asm/arch/sys_proto.h>
28 #include <asm/gpio.h>
29 #include <asm/arch/renesas.h>
30 #include <asm/arch/rcar-mstp.h>
31 #include <miiphy.h>
32 #include <i2c.h>
33 #include <mmc.h>
34 #include "qos.h"
35
36 DECLARE_GLOBAL_DATA_PTR;
37
38 #define CLK2MHZ(clk) (clk / 1000 / 1000)
s_init(void)39 void s_init(void)
40 {
41 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
42 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
43
44 /* Watchdog init */
45 writel(0xA5A5A500, &rwdt->rwtcsra);
46 writel(0xA5A5A500, &swdt->swtcsra);
47
48 /* CPU frequency setting. Set to 1.4GHz */
49 if (renesas_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) {
50 u32 stat = 0;
51 u32 stc = ((1400 / CLK2MHZ(get_board_sys_clk())) - 1)
52 << PLL0_STC_BIT;
53 clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
54
55 do {
56 stat = readl(PLLECR) & PLL0ST;
57 } while (stat == 0x0);
58 }
59
60 /* QoS(Quality-of-Service) Init */
61 qos_init();
62 }
63
64 #define TMU0_MSTP125 BIT(25)
65
66 #define SD1CKCR 0xE6150078
67 #define SD2CKCR 0xE615026C
68 #define SD_97500KHZ 0x7
69
board_early_init_f(void)70 int board_early_init_f(void)
71 {
72 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
73
74 /*
75 * SD0 clock is set to 97.5MHz by default.
76 * Set SD1 and SD2 to the 97.5MHz as well.
77 */
78 writel(SD_97500KHZ, SD1CKCR);
79 writel(SD_97500KHZ, SD2CKCR);
80
81 return 0;
82 }
83
84 #define ETHERNET_PHY_RESET 185 /* GPIO 5 31 */
85
board_init(void)86 int board_init(void)
87 {
88 /* adress of boot parameters */
89 gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
90
91 /* Force ethernet PHY out of reset */
92 gpio_request(ETHERNET_PHY_RESET, "phy_reset");
93 gpio_direction_output(ETHERNET_PHY_RESET, 0);
94 mdelay(10);
95 gpio_direction_output(ETHERNET_PHY_RESET, 1);
96
97 return 0;
98 }
99
dram_init(void)100 int dram_init(void)
101 {
102 if (fdtdec_setup_mem_size_base() != 0)
103 return -EINVAL;
104
105 return 0;
106 }
107
dram_init_banksize(void)108 int dram_init_banksize(void)
109 {
110 fdtdec_setup_memory_banksize();
111
112 return 0;
113 }
114
115 /* KSZ8041NL/RNL */
116 #define PHY_CONTROL1 0x1E
117 #define PHY_LED_MODE 0xC000
118 #define PHY_LED_MODE_ACK 0x4000
board_phy_config(struct phy_device * phydev)119 int board_phy_config(struct phy_device *phydev)
120 {
121 int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
122 ret &= ~PHY_LED_MODE;
123 ret |= PHY_LED_MODE_ACK;
124 ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
125
126 return 0;
127 }
128
reset_cpu(void)129 void reset_cpu(void)
130 {
131 struct udevice *dev;
132 const u8 pmic_bus = 2;
133 const u8 pmic_addr = 0x58;
134 u8 data;
135 int ret;
136
137 ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
138 if (ret)
139 hang();
140
141 ret = dm_i2c_read(dev, 0x13, &data, 1);
142 if (ret)
143 hang();
144
145 data |= BIT(1);
146
147 ret = dm_i2c_write(dev, 0x13, &data, 1);
148 if (ret)
149 hang();
150 }
151
env_get_location(enum env_operation op,int prio)152 enum env_location env_get_location(enum env_operation op, int prio)
153 {
154 const u32 load_magic = 0xb33fc0de;
155
156 /* Block environment access if loaded using JTAG */
157 if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
158 (op != ENVOP_INIT))
159 return ENVL_UNKNOWN;
160
161 if (prio)
162 return ENVL_UNKNOWN;
163
164 return ENVL_SPI_FLASH;
165 }
166