1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * board/renesas/stout/stout.c
4 * This file is Stout board support.
5 *
6 * Copyright (C) 2015 Renesas Electronics Europe GmbH
7 * Copyright (C) 2015 Renesas Electronics Corporation
8 * Copyright (C) 2015 Cogent Embedded, Inc.
9 */
10
11 #include <clock_legacy.h>
12 #include <env.h>
13 #include <init.h>
14 #include <malloc.h>
15 #include <netdev.h>
16 #include <dm.h>
17 #include <asm/global_data.h>
18 #include <dm/platform_data/serial_sh.h>
19 #include <env_internal.h>
20 #include <asm/processor.h>
21 #include <asm/mach-types.h>
22 #include <asm/io.h>
23 #include <linux/bitops.h>
24 #include <linux/delay.h>
25 #include <linux/errno.h>
26 #include <asm/arch/sys_proto.h>
27 #include <asm/gpio.h>
28 #include <asm/arch/renesas.h>
29 #include <asm/arch/rcar-mstp.h>
30 #include <miiphy.h>
31 #include <i2c.h>
32 #include <mmc.h>
33 #include "qos.h"
34 #include "cpld.h"
35
36 DECLARE_GLOBAL_DATA_PTR;
37
38 #define CLK2MHZ(clk) (clk / 1000 / 1000)
s_init(void)39 void s_init(void)
40 {
41 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
42 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
43
44 /* Watchdog init */
45 writel(0xA5A5A500, &rwdt->rwtcsra);
46 writel(0xA5A5A500, &swdt->swtcsra);
47
48 /* CPU frequency setting. Set to 1.4GHz */
49 if (renesas_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) {
50 u32 stat = 0;
51 u32 stc = ((1400 / CLK2MHZ(get_board_sys_clk())) - 1)
52 << PLL0_STC_BIT;
53 clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
54
55 do {
56 stat = readl(PLLECR) & PLL0ST;
57 } while (stat == 0x0);
58 }
59
60 /* QoS(Quality-of-Service) Init */
61 qos_init();
62 }
63
64 #define TMU0_MSTP125 BIT(25)
65
66 #define SD2CKCR 0xE6150078
67 #define SD2_97500KHZ 0x7
68
board_early_init_f(void)69 int board_early_init_f(void)
70 {
71 /* TMU0 */
72 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
73
74 /*
75 * SD0 clock is set to 97.5MHz by default.
76 * Set SD2 to the 97.5MHz as well.
77 */
78 writel(SD2_97500KHZ, SD2CKCR);
79
80 return 0;
81 }
82
83 #define ETHERNET_PHY_RESET 123 /* GPIO 3 31 */
84
board_init(void)85 int board_init(void)
86 {
87 /* adress of boot parameters */
88 gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
89
90 cpld_init();
91
92 /* Force ethernet PHY out of reset */
93 gpio_request(ETHERNET_PHY_RESET, "phy_reset");
94 gpio_direction_output(ETHERNET_PHY_RESET, 0);
95 mdelay(20);
96 gpio_direction_output(ETHERNET_PHY_RESET, 1);
97
98 return 0;
99 }
100
dram_init(void)101 int dram_init(void)
102 {
103 if (fdtdec_setup_mem_size_base() != 0)
104 return -EINVAL;
105
106 return 0;
107 }
108
dram_init_banksize(void)109 int dram_init_banksize(void)
110 {
111 fdtdec_setup_memory_banksize();
112
113 return 0;
114 }
115
116 /* Stout has KSZ8041NL/RNL */
117 #define PHY_CONTROL1 0x1E
118 #define PHY_LED_MODE 0xC000
119 #define PHY_LED_MODE_ACK 0x4000
board_phy_config(struct phy_device * phydev)120 int board_phy_config(struct phy_device *phydev)
121 {
122 int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
123 ret &= ~PHY_LED_MODE;
124 ret |= PHY_LED_MODE_ACK;
125 ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
126
127 return 0;
128 }
129
env_get_location(enum env_operation op,int prio)130 enum env_location env_get_location(enum env_operation op, int prio)
131 {
132 const u32 load_magic = 0xb33fc0de;
133
134 /* Block environment access if loaded using JTAG */
135 if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
136 (op != ENVOP_INIT))
137 return ENVL_UNKNOWN;
138
139 if (prio)
140 return ENVL_UNKNOWN;
141
142 return ENVL_SPI_FLASH;
143 }
144