1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Board functions for TI AM335X based draco board
4 * (C) Copyright 2013 Siemens Schweiz AG
5 * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
6 *
7 * Based on:
8 *
9 * Board functions for TI AM335X based boards
10 * u-boot:/board/ti/am335x/board.c
11 *
12 * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
13 */
14
15 #include <command.h>
16 #include <cpsw.h>
17 #include <env.h>
18 #include <init.h>
19 #include <linux/delay.h>
20 #include <nand.h>
21 #include <asm/arch/clock.h>
22 #include <asm/arch/ddr_defs.h>
23 #include <asm/arch/mem.h>
24 #include <asm/arch/sys_proto.h>
25 #include <asm/gpio.h>
26 #include <asm/io.h>
27 #include "board.h"
28 #include "../common/eeprom.h"
29 #include "../common/factoryset.h"
30
31 #ifdef CONFIG_XPL_BUILD
32 static struct draco_baseboard_id __section(".data") settings;
33
34 #if DDR_PLL_FREQ == 303
35 #if !defined(CONFIG_TARGET_ETAMIN)
36 /* Default@303MHz-i0 */
37 const struct ddr3_data ddr3_default = {
38 0x33524444, 0x56312e35, 0x0080, 0x0000, 0x003A, 0x003F, 0x009F,
39 0x0079, 0x0888A39B, 0x26517FDA, 0x501F84EF, 0x00100206, 0x61A44A32,
40 0x0000093B, 0x0000014A,
41 "default name @303MHz \0",
42 "default marking \0",
43 };
44 #else
45 /* etamin board */
46 const struct ddr3_data ddr3_default = {
47 0x33524444, 0x56312e36, 0x0080, 0x0000, 0x003A, 0x0010, 0x009F,
48 0x0050, 0x0888A39B, 0x266D7FDA, 0x501F86AF, 0x00100206, 0x61A44BB2,
49 0x0000093B, 0x0000018A,
50 "test-etamin \0",
51 "generic-8Gbit \0",
52 };
53 #endif
54 #elif DDR_PLL_FREQ == 400
55 /* Default@400MHz-i0 */
56 const struct ddr3_data ddr3_default = {
57 0x33524444, 0x56312e35, 0x0080, 0x0000, 0x0039, 0x0046, 0x00ab,
58 0x0080, 0x0AAAA4DB, 0x26307FDA, 0x501F821F, 0x00100207, 0x61A45232,
59 0x00000618, 0x0000014A,
60 "default name @400MHz \0",
61 "default marking \0",
62 };
63 #endif
64
set_default_ddr3_timings(void)65 static void set_default_ddr3_timings(void)
66 {
67 printf("Set default DDR3 settings\n");
68 settings.ddr3 = ddr3_default;
69 }
70
print_ddr3_timings(void)71 static void print_ddr3_timings(void)
72 {
73 printf("\nDDR3\n");
74 printf("clock:\t\t%d MHz\n", DDR_PLL_FREQ);
75 printf("device:\t\t%s\n", settings.ddr3.manu_name);
76 printf("marking:\t%s\n", settings.ddr3.manu_marking);
77 printf("%-20s, %-8s, %-8s, %-4s\n", "timing parameters", "eeprom",
78 "default", "diff");
79 PRINTARGS(magic);
80 PRINTARGS(version);
81 PRINTARGS(ddr3_sratio);
82 PRINTARGS(iclkout);
83
84 PRINTARGS(dt0rdsratio0);
85 PRINTARGS(dt0wdsratio0);
86 PRINTARGS(dt0fwsratio0);
87 PRINTARGS(dt0wrsratio0);
88
89 PRINTARGS(sdram_tim1);
90 PRINTARGS(sdram_tim2);
91 PRINTARGS(sdram_tim3);
92
93 PRINTARGS(emif_ddr_phy_ctlr_1);
94
95 PRINTARGS(sdram_config);
96 PRINTARGS(ref_ctrl);
97 PRINTARGS(ioctr_val);
98 }
99
print_chip_data(void)100 static void print_chip_data(void)
101 {
102 struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
103 dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
104 printf("\nCPU BOARD\n");
105 printf("device: \t'%s'\n", settings.chip.sdevname);
106 printf("hw version: \t'%s'\n", settings.chip.shwver);
107 printf("max freq: \t%d MHz\n", dpll_mpu_opp100.m);
108 }
109 #endif /* CONFIG_XPL_BUILD */
110
111 #define AM335X_NAND_ECC_MASK 0x0f
112 #define AM335X_NAND_ECC_TYPE_16 0x02
113
114 static int ecc_type;
115
116 struct am335x_nand_geometry {
117 u32 magic;
118 u8 nand_geo_addr;
119 u8 nand_geo_page;
120 u8 nand_bus;
121 };
122
draco_read_nand_geometry(void)123 static int draco_read_nand_geometry(void)
124 {
125 struct am335x_nand_geometry geo;
126
127 /* Read NAND geometry */
128 if (siemens_ee_read_data(SIEMENS_EE_ADDR_NAND_GEO, (uchar *)&geo,
129 sizeof(struct am335x_nand_geometry))) {
130 printf("Could not read the NAND geomtery; something fundamentally wrong on the I2C bus.\n");
131 return -EIO;
132 }
133 if (geo.magic != 0xa657b310) {
134 printf("%s: bad magic: %x\n", __func__, geo.magic);
135 return -EFAULT;
136 }
137 if ((geo.nand_bus & AM335X_NAND_ECC_MASK) == AM335X_NAND_ECC_TYPE_16)
138 ecc_type = 16;
139 else
140 ecc_type = 8;
141
142 return 0;
143 }
144
145 #ifdef CONFIG_XPL_BUILD
146 /*
147 * Read header information from EEPROM into global structure.
148 */
draco_read_eeprom(void)149 int draco_read_eeprom(void)
150 {
151 /* Read Siemens eeprom data (DDR3) */
152 if (siemens_ee_read_data(SIEMENS_EE_ADDR_DDR3, (uchar *)&settings.ddr3,
153 sizeof(struct ddr3_data))) {
154 printf("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\nUse default DDR3 timings\n");
155 set_default_ddr3_timings();
156 }
157 /* Read Siemens eeprom data (CHIP) */
158 if (siemens_ee_read_data(SIEMENS_EE_ADDR_CHIP, (uchar *)&settings.chip,
159 sizeof(settings.chip)))
160 printf("Could not read chip settings\n");
161
162 if (ddr3_default.magic == settings.ddr3.magic &&
163 ddr3_default.version == settings.ddr3.version) {
164 printf("Using DDR3 settings from EEPROM\n");
165 } else {
166 if (ddr3_default.magic != settings.ddr3.magic)
167 printf("Warning: No valid DDR3 data in eeprom.\n");
168 if (ddr3_default.version != settings.ddr3.version)
169 printf("Warning: DDR3 data version does not match.\n");
170
171 printf("Using default settings\n");
172 set_default_ddr3_timings();
173 }
174
175 if (MAGIC_CHIP == settings.chip.magic)
176 print_chip_data();
177 else
178 printf("Warning: No chip data in eeprom\n");
179
180 print_ddr3_timings();
181
182 return draco_read_nand_geometry();
183 }
184
draco_init_ddr(void)185 void draco_init_ddr(void)
186 {
187 struct emif_regs draco_ddr3_emif_reg_data = {
188 .zq_config = 0x50074BE4,
189 };
190
191 struct ddr_data draco_ddr3_data = {
192 };
193
194 struct cmd_control draco_ddr3_cmd_ctrl_data = {
195 };
196
197 struct ctrl_ioregs draco_ddr3_ioregs = {
198 };
199
200 /* pass values from eeprom */
201 draco_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1;
202 draco_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2;
203 draco_ddr3_emif_reg_data.sdram_tim3 = settings.ddr3.sdram_tim3;
204 draco_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 =
205 settings.ddr3.emif_ddr_phy_ctlr_1;
206 draco_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config;
207 draco_ddr3_emif_reg_data.sdram_config2 = 0x08000000;
208 draco_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl;
209
210 draco_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0;
211 draco_ddr3_data.datawdsratio0 = settings.ddr3.dt0wdsratio0;
212 draco_ddr3_data.datafwsratio0 = settings.ddr3.dt0fwsratio0;
213 draco_ddr3_data.datawrsratio0 = settings.ddr3.dt0wrsratio0;
214
215 draco_ddr3_cmd_ctrl_data.cmd0csratio = settings.ddr3.ddr3_sratio;
216 draco_ddr3_cmd_ctrl_data.cmd0iclkout = settings.ddr3.iclkout;
217 draco_ddr3_cmd_ctrl_data.cmd1csratio = settings.ddr3.ddr3_sratio;
218 draco_ddr3_cmd_ctrl_data.cmd1iclkout = settings.ddr3.iclkout;
219 draco_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio;
220 draco_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout;
221
222 draco_ddr3_ioregs.cm0ioctl = settings.ddr3.ioctr_val,
223 draco_ddr3_ioregs.cm1ioctl = settings.ddr3.ioctr_val,
224 draco_ddr3_ioregs.cm2ioctl = settings.ddr3.ioctr_val,
225 draco_ddr3_ioregs.dt0ioctl = settings.ddr3.ioctr_val,
226 draco_ddr3_ioregs.dt1ioctl = settings.ddr3.ioctr_val,
227
228 config_ddr(DDR_PLL_FREQ, &draco_ddr3_ioregs, &draco_ddr3_data,
229 &draco_ddr3_cmd_ctrl_data, &draco_ddr3_emif_reg_data, 0);
230 }
231
spl_draco_board_init(void)232 void spl_draco_board_init(void)
233 {
234 return;
235 }
236 #endif /* if def CONFIG_XPL_BUILD */
237
238 #ifdef CONFIG_BOARD_LATE_INIT
board_late_init(void)239 int board_late_init(void)
240 {
241 int ret;
242
243 ret = draco_read_nand_geometry();
244 if (ret != 0)
245 return ret;
246
247 nand_curr_device = 0;
248 omap_nand_switch_ecc(1, ecc_type);
249 #ifdef CONFIG_TARGET_ETAMIN
250 nand_curr_device = 1;
251 omap_nand_switch_ecc(1, ecc_type);
252 #endif
253 #ifdef CONFIG_FACTORYSET
254 /* Set ASN in environment*/
255 if (factory_dat.asn[0] != 0) {
256 env_set("dtb_name", (char *)factory_dat.asn);
257 } else {
258 /* dtb suffix gets added in load script */
259 env_set("dtb_name", "am335x-draco");
260 }
261 #else
262 env_set("dtb_name", "am335x-draco");
263 #endif
264
265 return 0;
266 }
267 #endif
268
269 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_XPL_BUILD)) || \
270 (defined(CONFIG_SPL_ETH) && defined(CONFIG_XPL_BUILD))
cpsw_control(int enabled)271 static void cpsw_control(int enabled)
272 {
273 /* VTP can be added here */
274
275 return;
276 }
277
278 static struct cpsw_slave_data cpsw_slaves[] = {
279 {
280 .slave_reg_ofs = 0x208,
281 .sliver_reg_ofs = 0xd80,
282 .phy_addr = 0,
283 .phy_if = PHY_INTERFACE_MODE_MII,
284 },
285 };
286
287 static struct cpsw_platform_data cpsw_data = {
288 .mdio_base = CPSW_MDIO_BASE,
289 .cpsw_base = CPSW_BASE,
290 .mdio_div = 0xff,
291 .channels = 4,
292 .cpdma_reg_ofs = 0x800,
293 .slaves = 1,
294 .slave_data = cpsw_slaves,
295 .ale_reg_ofs = 0xd00,
296 .ale_entries = 1024,
297 .host_port_reg_ofs = 0x108,
298 .hw_stats_reg_ofs = 0x900,
299 .bd_ram_ofs = 0x2000,
300 .mac_control = (1 << 5),
301 .control = cpsw_control,
302 .host_port_num = 0,
303 .version = CPSW_CTRL_VERSION_2,
304 };
305
306 #if defined(CONFIG_DRIVER_TI_CPSW) || \
307 (defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET))
board_eth_init(struct bd_info * bis)308 int board_eth_init(struct bd_info *bis)
309 {
310 struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
311 int n = 0;
312 int rv;
313
314 factoryset_env_set();
315
316 /* Set rgmii mode and enable rmii clock to be sourced from chip */
317 writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
318
319 rv = cpsw_register(&cpsw_data);
320 if (rv < 0)
321 printf("Error %d registering CPSW switch\n", rv);
322 else
323 n += rv;
324 return n;
325 }
326
do_switch_reset(struct cmd_tbl * cmdtp,int flag,int argc,char * const argv[])327 static int do_switch_reset(struct cmd_tbl *cmdtp, int flag, int argc,
328 char *const argv[])
329 {
330 /* Reset SMSC LAN9303 switch for default configuration */
331 gpio_request(GPIO_LAN9303_NRST, "nRST");
332 gpio_direction_output(GPIO_LAN9303_NRST, 0);
333 /* assert active low reset for 200us */
334 udelay(200);
335 gpio_set_value(GPIO_LAN9303_NRST, 1);
336
337 return 0;
338 };
339
340 U_BOOT_CMD(
341 switch_rst, CONFIG_SYS_MAXARGS, 1, do_switch_reset,
342 "Reset LAN9303 switch via its reset pin",
343 ""
344 );
345 #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
346 #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_XPL_BUILD)) */
347