1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2016 samtec automotive software & electronics gmbh
4 * Copyright (C) 2017-2019 softing automotive electronics gmbH
5 *
6 * Author: Christoph Fritz <chf.fritz@googlemail.com>
7 */
8
9 #include <init.h>
10 #include <net.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/crm_regs.h>
13 #include <asm/arch/iomux.h>
14 #include <asm/arch/imx-regs.h>
15 #include <asm/arch/mx6-pins.h>
16 #include <asm/arch/sys_proto.h>
17 #include <asm/global_data.h>
18 #include <asm/gpio.h>
19 #include <asm/mach-imx/iomux-v3.h>
20 #include <asm/io.h>
21 #include <asm/sections.h>
22 #include <env.h>
23 #include <linux/bitops.h>
24 #include <linux/delay.h>
25 #include <linux/sizes.h>
26 #include <config.h>
27 #include <fsl_esdhc_imx.h>
28 #include <mmc.h>
29 #include <miiphy.h>
30 #include <netdev.h>
31 #include <power/pmic.h>
32 #include <power/pfuze100_pmic.h>
33 #include <usb.h>
34 #include <usb/ehci-ci.h>
35 #include <pwm.h>
36 #include <wait_bit.h>
37
38 DECLARE_GLOBAL_DATA_PTR;
39
40 #define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
41 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
42 PAD_CTL_SRE_FAST)
43
44 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PKE | \
45 PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | \
46 PAD_CTL_SRE_FAST)
47
48 #define ENET_CLK_PAD_CTRL PAD_CTL_DSE_34ohm
49
50 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | \
51 PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_HIGH | \
52 PAD_CTL_SRE_FAST)
53
54 #define USDHC_CLK_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
55 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST)
56
57 #define USDHC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
58 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm | \
59 PAD_CTL_SRE_FAST)
60
61 #define USDHC_RESET_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
62 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm)
63
64 #define GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
65 PAD_CTL_PKE)
66
dram_init(void)67 int dram_init(void)
68 {
69 gd->ram_size = imx_ddr_size();
70
71 return 0;
72 }
73
74 static iomux_v3_cfg_t const pwm_led_pads[] = {
75 MX6_PAD_RGMII2_RD2__PWM2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* green */
76 MX6_PAD_RGMII2_TD2__PWM6_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* red */
77 MX6_PAD_RGMII2_RD3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* blue */
78 };
79
board_net_init(void)80 static int board_net_init(void)
81 {
82 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
83 unsigned char eth1addr[6];
84 int ret;
85
86 /* just to get second mac address */
87 imx_get_mac_from_fuse(1, eth1addr);
88 if (!env_get("eth1addr") && is_valid_ethaddr(eth1addr))
89 eth_env_set_enetaddr("eth1addr", eth1addr);
90
91 /*
92 * Generate phy reference clock via pin IOMUX ENET_REF_CLK1/2 by erasing
93 * ENET1/2_TX_CLK_DIR gpr1[14:13], so that reference clock is driven by
94 * ref_enetpll0/1 and enable ENET1/2_TX_CLK output driver.
95 */
96 clrsetbits_le32(&iomuxc_regs->gpr[1],
97 IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK |
98 IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK,
99 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK |
100 IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
101
102 ret = enable_fec_anatop_clock(0, ENET_50MHZ);
103 if (ret)
104 goto eth_fail;
105
106 ret = enable_fec_anatop_clock(1, ENET_50MHZ);
107 if (ret)
108 goto eth_fail;
109
110 return ret;
111
112 eth_fail:
113 printf("FEC MXC: %s:failed (%i)\n", __func__, ret);
114 return ret;
115 }
116
pfuze_init(unsigned char i2cbus)117 static struct pmic *pfuze_init(unsigned char i2cbus)
118 {
119 struct pmic *p;
120 int ret;
121 u32 reg;
122
123 ret = power_pfuze100_init(i2cbus);
124 if (ret)
125 return NULL;
126
127 p = pmic_get("PFUZE100");
128 ret = pmic_probe(p);
129 if (ret)
130 return NULL;
131
132 pmic_reg_read(p, PFUZE100_DEVICEID, ®);
133 printf("PMIC: PFUZE%i00 ID=0x%02x\n", (reg & 1) ? 2 : 1, reg);
134
135 /* Set SW1AB stanby volage to 0.975V */
136 pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®);
137 reg &= ~SW1x_STBY_MASK;
138 reg |= SW1x_0_975V;
139 pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
140
141 /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
142 pmic_reg_read(p, PFUZE100_SW1ABCONF, ®);
143 reg &= ~SW1xCONF_DVSSPEED_MASK;
144 reg |= SW1xCONF_DVSSPEED_4US;
145 pmic_reg_write(p, PFUZE100_SW1ABCONF, reg);
146
147 /* Set SW1C standby voltage to 0.975V */
148 pmic_reg_read(p, PFUZE100_SW1CSTBY, ®);
149 reg &= ~SW1x_STBY_MASK;
150 reg |= SW1x_0_975V;
151 pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
152
153 /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
154 pmic_reg_read(p, PFUZE100_SW1CCONF, ®);
155 reg &= ~SW1xCONF_DVSSPEED_MASK;
156 reg |= SW1xCONF_DVSSPEED_4US;
157 pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
158
159 return p;
160 }
161
pfuze_mode_init(struct pmic * p,u32 mode)162 static int pfuze_mode_init(struct pmic *p, u32 mode)
163 {
164 unsigned char offset, i, switch_num;
165 u32 id;
166 int ret;
167
168 pmic_reg_read(p, PFUZE100_DEVICEID, &id);
169 id = id & 0xf;
170
171 if (id == 0) {
172 switch_num = 6;
173 offset = PFUZE100_SW1CMODE;
174 } else if (id == 1) {
175 switch_num = 4;
176 offset = PFUZE100_SW2MODE;
177 } else {
178 printf("Not supported, id=%d\n", id);
179 return -EINVAL;
180 }
181
182 ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode);
183 if (ret < 0) {
184 printf("Set SW1AB mode error!\n");
185 return ret;
186 }
187
188 for (i = 0; i < switch_num - 1; i++) {
189 ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode);
190 if (ret < 0) {
191 printf("Set switch 0x%x mode error!\n",
192 offset + i * SWITCH_SIZE);
193 return ret;
194 }
195 }
196
197 return ret;
198 }
199
power_init_board(void)200 int power_init_board(void)
201 {
202 struct pmic *p;
203 int ret;
204
205 p = pfuze_init(I2C_PMIC);
206 if (!p)
207 return -ENODEV;
208
209 ret = pfuze_mode_init(p, APS_PFM);
210 if (ret < 0)
211 return ret;
212
213 set_ldo_voltage(LDO_ARM, 1175); /* Set VDDARM to 1.175V */
214 set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
215
216 return 0;
217 }
218
219 #ifdef CONFIG_USB_EHCI_MX6
220 static iomux_v3_cfg_t const usb_otg_pads[] = {
221 /* OGT1 */
222 MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
223 MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
224 /* OTG2 */
225 MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
226 };
227
setup_iomux_usb(void)228 static void setup_iomux_usb(void)
229 {
230 imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
231 ARRAY_SIZE(usb_otg_pads));
232 }
233
board_usb_phy_mode(int port)234 int board_usb_phy_mode(int port)
235 {
236 if (port == 1)
237 return USB_INIT_HOST;
238 else
239 return usb_phy_mode(port);
240 }
241 #endif
242
243 #ifdef CONFIG_PWM_IMX
set_pwm_leds(void)244 static int set_pwm_leds(void)
245 {
246 int ret;
247
248 imx_iomux_v3_setup_multiple_pads(pwm_led_pads,
249 ARRAY_SIZE(pwm_led_pads));
250 /* enable backlight PWM 2, green LED */
251 ret = pwm_init(1, 0, 0);
252 if (ret)
253 goto error;
254 /* duty cycle 200ns, period: 8000ns */
255 ret = pwm_config(1, 200, 8000);
256 if (ret)
257 goto error;
258 ret = pwm_enable(1);
259 if (ret)
260 goto error;
261
262 /* enable backlight PWM 1, blue LED */
263 ret = pwm_init(0, 0, 0);
264 if (ret)
265 goto error;
266 /* duty cycle 200ns, period: 8000ns */
267 ret = pwm_config(0, 200, 8000);
268 if (ret)
269 goto error;
270 ret = pwm_enable(0);
271 if (ret)
272 goto error;
273
274 /* enable backlight PWM 6, red LED */
275 ret = pwm_init(5, 0, 0);
276 if (ret)
277 goto error;
278 /* duty cycle 200ns, period: 8000ns */
279 ret = pwm_config(5, 200, 8000);
280 if (ret)
281 goto error;
282 ret = pwm_enable(5);
283
284 error:
285 return ret;
286 }
287 #else
set_pwm_leds(void)288 static int set_pwm_leds(void)
289 {
290 return 0;
291 }
292 #endif
293
294 #define ADCx_HC0 0x00
295 #define ADCx_HS 0x08
296 #define ADCx_HS_C0 BIT(0)
297 #define ADCx_R0 0x0c
298 #define ADCx_CFG 0x14
299 #define ADCx_CFG_SWMODE 0x308
300 #define ADCx_GC 0x18
301 #define ADCx_GC_CAL BIT(7)
302
read_adc(u32 * val)303 static int read_adc(u32 *val)
304 {
305 int ret;
306 void __iomem *b = map_physmem(ADC1_BASE_ADDR, 0x100, MAP_NOCACHE);
307
308 /* use software mode */
309 writel(ADCx_CFG_SWMODE, b + ADCx_CFG);
310
311 /* start auto calibration */
312 setbits_le32(b + ADCx_GC, ADCx_GC_CAL);
313 ret = wait_for_bit_le32(b + ADCx_GC, ADCx_GC_CAL, ADCx_GC_CAL, 10, 0);
314 if (ret)
315 goto adc_exit;
316
317 /* start conversion */
318 writel(0, b + ADCx_HC0);
319
320 /* wait for conversion */
321 ret = wait_for_bit_le32(b + ADCx_HS, ADCx_HS_C0, ADCx_HS_C0, 10, 0);
322 if (ret)
323 goto adc_exit;
324
325 /* read result */
326 *val = readl(b + ADCx_R0);
327
328 adc_exit:
329 if (ret)
330 printf("ADC failure (ret=%i)\n", ret);
331 unmap_physmem(b, MAP_NOCACHE);
332 return ret;
333 }
334
335 #define VAL_UPPER 2498
336 #define VAL_LOWER 1550
337
set_pin_state(void)338 static int set_pin_state(void)
339 {
340 u32 val;
341 int ret;
342
343 ret = read_adc(&val);
344 if (ret)
345 return ret;
346
347 if (val >= VAL_UPPER)
348 env_set("pin_state", "connected");
349 else if (val < VAL_UPPER && val > VAL_LOWER)
350 env_set("pin_state", "open");
351 else
352 env_set("pin_state", "button");
353
354 return ret;
355 }
356
board_late_init(void)357 int board_late_init(void)
358 {
359 int ret;
360
361 ret = set_pwm_leds();
362 if (ret)
363 return ret;
364
365 ret = set_pin_state();
366
367 return ret;
368 }
369
board_early_init_f(void)370 int board_early_init_f(void)
371 {
372 setup_iomux_usb();
373
374 return 0;
375 }
376
board_init(void)377 int board_init(void)
378 {
379 /* Address of boot parameters */
380 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
381
382 return board_net_init();
383 }
384
checkboard(void)385 int checkboard(void)
386 {
387 puts("Board: VIN|ING 2000\n");
388
389 return 0;
390 }
391
392 #define PCIE_PHY_PUP_REQ BIT(7)
393
board_preboot_os(void)394 void board_preboot_os(void)
395 {
396 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
397 struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR;
398
399 /* Bring the PCI power domain up, so that old vendorkernel works. */
400 setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
401 setbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
402 setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ);
403 }
404
405 #ifdef CONFIG_XPL_BUILD
406 #include <linux/libfdt.h>
407 #include <spl.h>
408 #include <asm/arch/mx6-ddr.h>
409
410 static iomux_v3_cfg_t const pcie_pads[] = {
411 MX6_PAD_NAND_DATA02__GPIO4_IO_6 | MUX_PAD_CTRL(GPIO_PAD_CTRL),
412 };
413
414 static iomux_v3_cfg_t const uart_pads[] = {
415 MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
416 MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
417 };
418
419 static iomux_v3_cfg_t const usdhc4_pads[] = {
420 MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
421 MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
422 MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
423 MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
424 MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
425 MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
426 MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
427 MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
428 MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
429 MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
430 };
431
vining2000_spl_setup_iomux_pcie(void)432 static void vining2000_spl_setup_iomux_pcie(void)
433 {
434 imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
435 }
436
vining2000_spl_setup_iomux_uart(void)437 static void vining2000_spl_setup_iomux_uart(void)
438 {
439 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
440 }
441
442 static struct fsl_esdhc_cfg usdhc_cfg = { USDHC4_BASE_ADDR };
443
board_mmc_init(struct bd_info * bis)444 int board_mmc_init(struct bd_info *bis)
445 {
446 imx_iomux_v3_setup_multiple_pads(usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
447
448 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
449 gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk;
450 return fsl_esdhc_initialize(bis, &usdhc_cfg);
451 }
452
board_mmc_getcd(struct mmc * mmc)453 int board_mmc_getcd(struct mmc *mmc)
454 {
455 return 1;
456 }
457
458 const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
459 .dram_dqm0 = 0x00000028,
460 .dram_dqm1 = 0x00000028,
461 .dram_dqm2 = 0x00000028,
462 .dram_dqm3 = 0x00000028,
463 .dram_ras = 0x00000028,
464 .dram_cas = 0x00000028,
465 .dram_odt0 = 0x00000028,
466 .dram_odt1 = 0x00000028,
467 .dram_sdba2 = 0x00000000,
468 .dram_sdcke0 = 0x00003000,
469 .dram_sdcke1 = 0x00003000,
470 .dram_sdclk_0 = 0x00000030,
471 .dram_sdqs0 = 0x00000028,
472 .dram_sdqs1 = 0x00000028,
473 .dram_sdqs2 = 0x00000028,
474 .dram_sdqs3 = 0x00000028,
475 .dram_reset = 0x00000028,
476 };
477
478 const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = {
479 .grp_addds = 0x00000028,
480 .grp_b0ds = 0x00000028,
481 .grp_b1ds = 0x00000028,
482 .grp_b2ds = 0x00000028,
483 .grp_b3ds = 0x00000028,
484 .grp_ctlds = 0x00000028,
485 .grp_ddr_type = 0x000c0000,
486 .grp_ddrmode = 0x00020000,
487 .grp_ddrmode_ctl = 0x00020000,
488 .grp_ddrpke = 0x00000000,
489 };
490
491 const struct mx6_mmdc_calibration mx6_mmcd_calib = {
492 .p0_mpwldectrl0 = 0x0022001C,
493 .p0_mpwldectrl1 = 0x001F001A,
494 .p0_mpdgctrl0 = 0x01380134,
495 .p0_mpdgctrl1 = 0x0124011C,
496 .p0_mprddlctl = 0x42404444,
497 .p0_mpwrdlctl = 0x36383C38,
498 };
499
500 static struct mx6_ddr3_cfg mem_ddr = {
501 .mem_speed = 1600,
502 .density = 4,
503 .width = 32,
504 .banks = 8,
505 .rowaddr = 15,
506 .coladdr = 10,
507 .pagesz = 2,
508 .trcd = 1391,
509 .trcmin = 4875,
510 .trasmin = 3500,
511 };
512
ccgr_init(void)513 static void ccgr_init(void)
514 {
515 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
516
517 writel(0xF000000F, &ccm->CCGR0); /* AIPS_TZ{1,2,3} */
518 writel(0x303C0000, &ccm->CCGR1); /* GPT, OCRAM */
519 writel(0x00FFFCC0, &ccm->CCGR2); /* IPMUX, I2C1, I2C3 */
520 writel(0x3F300030, &ccm->CCGR3); /* OCRAM, MMDC, ENET */
521 writel(0x0000C003, &ccm->CCGR4); /* PCI, PL301 */
522 writel(0x0F0330C3, &ccm->CCGR5); /* UART, ROM */
523 writel(0x00000F00, &ccm->CCGR6); /* SDHI4, EIM */
524 }
525
vining2000_spl_dram_init(void)526 static void vining2000_spl_dram_init(void)
527 {
528 struct mx6_ddr_sysinfo sysinfo = {
529 .dsize = mem_ddr.width / 32,
530 .cs_density = 24,
531 .ncs = 1,
532 .cs1_mirror = 0,
533 .rtt_wr = 1, /* RTT_wr = RZQ/4 */
534 .rtt_nom = 1, /* RTT_Nom = RZQ/4 */
535 .walat = 1, /* Write additional latency */
536 .ralat = 5, /* Read additional latency */
537 .mif3_mode = 3, /* Command prediction working mode */
538 .bi_on = 1, /* Bank interleaving enabled */
539 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
540 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
541 .ddr_type = DDR_TYPE_DDR3,
542 .refsel = 1, /* Refresh cycles at 32KHz */
543 .refr = 7, /* 8 refresh commands per refresh cycle */
544 };
545
546 mx6sx_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
547 mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
548
549 /* Perform DDR DRAM calibration */
550 udelay(100);
551 mmdc_do_write_level_calibration(&sysinfo);
552 mmdc_do_dqs_calibration(&sysinfo);
553 }
554
board_init_f(ulong dummy)555 void board_init_f(ulong dummy)
556 {
557 /* setup AIPS and disable watchdog */
558 arch_cpu_init();
559
560 ccgr_init();
561
562 /* iomux setup */
563 vining2000_spl_setup_iomux_pcie();
564 vining2000_spl_setup_iomux_uart();
565
566 /* setup GP timer */
567 timer_init();
568
569 /* reset the PCIe device */
570 gpio_set_value(IMX_GPIO_NR(4, 6), 1);
571 udelay(50);
572 gpio_set_value(IMX_GPIO_NR(4, 6), 0);
573
574 /* UART clocks enabled and gd valid - init serial console */
575 preloader_console_init();
576
577 /* DDR initialization */
578 vining2000_spl_dram_init();
579
580 /* Clear the BSS. */
581 memset(__bss_start, 0, __bss_end - __bss_start);
582
583 /* load/boot image from boot device */
584 board_init_r(NULL, 0);
585 }
586 #endif
587