1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
4 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
5 *
6 * (C) Copyright 2007-2011
7 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
8 * Tom Cubie <tangliang@allwinnertech.com>
9 *
10 * Some board init for the Allwinner A10-evb board.
11 */
12
13 #include <clock_legacy.h>
14 #include <dm.h>
15 #include <env.h>
16 #include <hang.h>
17 #include <i2c.h>
18 #include <image.h>
19 #include <init.h>
20 #include <log.h>
21 #include <mmc.h>
22 #include <axp_pmic.h>
23 #include <generic-phy.h>
24 #include <phy-sun4i-usb.h>
25 #include <asm/arch/clock.h>
26 #include <asm/arch/cpu.h>
27 #include <asm/arch/display.h>
28 #include <asm/arch/dram.h>
29 #include <asm/arch/mmc.h>
30 #include <asm/arch/prcm.h>
31 #include <asm/arch/pmic_bus.h>
32 #include <asm/arch/spl.h>
33 #include <asm/arch/sys_proto.h>
34 #include <asm/global_data.h>
35 #include <linux/delay.h>
36 #include <linux/printk.h>
37 #include <linux/types.h>
38 #ifndef CONFIG_ARM64
39 #include <asm/armv7.h>
40 #endif
41 #include <asm/gpio.h>
42 #include <sunxi_gpio.h>
43 #include <asm/io.h>
44 #include <u-boot/crc.h>
45 #include <env_internal.h>
46 #include <linux/libfdt.h>
47 #include <fdt_support.h>
48 #include <nand.h>
49 #include <net.h>
50 #include <spl.h>
51 #include <sy8106a.h>
52 #include <asm/setup.h>
53 #include <status_led.h>
54
55 DECLARE_GLOBAL_DATA_PTR;
56
i2c_init_board(void)57 void i2c_init_board(void)
58 {
59 #ifdef CONFIG_I2C0_ENABLE
60 #if defined(CONFIG_MACH_SUN4I) || \
61 defined(CONFIG_MACH_SUN5I) || \
62 defined(CONFIG_MACH_SUN7I) || \
63 defined(CONFIG_MACH_SUN8I_R40)
64 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
65 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
66 clock_twi_onoff(0, 1);
67 #elif defined(CONFIG_MACH_SUN6I)
68 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
69 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
70 clock_twi_onoff(0, 1);
71 #elif defined(CONFIG_MACH_SUN8I_V3S)
72 sunxi_gpio_set_cfgpin(SUNXI_GPB(6), SUN8I_V3S_GPB_TWI0);
73 sunxi_gpio_set_cfgpin(SUNXI_GPB(7), SUN8I_V3S_GPB_TWI0);
74 clock_twi_onoff(0, 1);
75 #elif defined(CONFIG_MACH_SUN8I)
76 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
77 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
78 clock_twi_onoff(0, 1);
79 #elif defined(CONFIG_MACH_SUN50I)
80 sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_GPH_TWI0);
81 sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_GPH_TWI0);
82 clock_twi_onoff(0, 1);
83 #endif
84 #endif
85
86 #ifdef CONFIG_I2C1_ENABLE
87 #if defined(CONFIG_MACH_SUN4I) || \
88 defined(CONFIG_MACH_SUN7I) || \
89 defined(CONFIG_MACH_SUN8I_R40)
90 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
91 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
92 clock_twi_onoff(1, 1);
93 #elif defined(CONFIG_MACH_SUN5I)
94 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
95 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
96 clock_twi_onoff(1, 1);
97 #elif defined(CONFIG_MACH_SUN6I)
98 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
99 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
100 clock_twi_onoff(1, 1);
101 #elif defined(CONFIG_MACH_SUN8I)
102 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
103 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
104 clock_twi_onoff(1, 1);
105 #elif defined(CONFIG_MACH_SUN50I)
106 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN50I_GPH_TWI1);
107 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN50I_GPH_TWI1);
108 clock_twi_onoff(1, 1);
109 #endif
110 #endif
111
112 #ifdef CONFIG_R_I2C_ENABLE
113 #ifdef CONFIG_MACH_SUN50I
114 clock_twi_onoff(5, 1);
115 sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI);
116 sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI);
117 #elif defined(CONFIG_MACH_SUN50I_H616)
118 clock_twi_onoff(5, 1);
119 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN50I_H616_GPL_R_TWI);
120 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN50I_H616_GPL_R_TWI);
121 #elif CONFIG_MACH_SUN55I_A523
122 clock_twi_onoff(5, 1);
123 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN50I_GPL_R_TWI);
124 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN50I_GPL_R_TWI);
125 #else
126 clock_twi_onoff(5, 1);
127 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
128 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
129 #endif
130 #endif
131 }
132
133 /*
134 * Try to use the environment from the boot source first.
135 * For MMC, this means a FAT partition on the boot device (SD or eMMC).
136 * If the raw MMC environment is also enabled, this is tried next.
137 * When booting from NAND we try UBI first, then NAND directly.
138 * SPI flash falls back to FAT (on SD card).
139 */
env_get_location(enum env_operation op,int prio)140 enum env_location env_get_location(enum env_operation op, int prio)
141 {
142 if (prio > 1)
143 return ENVL_UNKNOWN;
144
145 /* NOWHERE is exclusive, no other option can be defined. */
146 if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE))
147 return ENVL_NOWHERE;
148
149 switch (sunxi_get_boot_device()) {
150 case BOOT_DEVICE_MMC1:
151 case BOOT_DEVICE_MMC2:
152 if (prio == 0 && IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
153 return ENVL_FAT;
154 if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC))
155 return ENVL_MMC;
156 break;
157 case BOOT_DEVICE_NAND:
158 if (prio == 0 && IS_ENABLED(CONFIG_ENV_IS_IN_UBI))
159 return ENVL_UBI;
160 if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
161 return ENVL_NAND;
162 break;
163 case BOOT_DEVICE_SPI:
164 if (prio == 0 && IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
165 return ENVL_SPI_FLASH;
166 if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
167 return ENVL_FAT;
168 break;
169 case BOOT_DEVICE_BOARD:
170 break;
171 default:
172 break;
173 }
174
175 /*
176 * If we come here for the first time, we *must* return a valid
177 * environment location other than ENVL_UNKNOWN, or the setup sequence
178 * in board_f() will silently hang. This is arguably a bug in
179 * env_init(), but for now pick one environment for which we know for
180 * sure to have a driver for. For all defconfigs this is either FAT
181 * or UBI, or NOWHERE, which is already handled above.
182 */
183 if (prio == 0) {
184 if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
185 return ENVL_FAT;
186 if (IS_ENABLED(CONFIG_ENV_IS_IN_UBI))
187 return ENVL_UBI;
188 }
189
190 return ENVL_UNKNOWN;
191 }
192
193 /* called only from U-Boot proper */
board_init(void)194 int board_init(void)
195 {
196 __maybe_unused int id_pfr1, ret;
197
198 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
199
200 #if !defined(CONFIG_ARM64) && !defined(CONFIG_MACH_SUNIV)
201 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
202 debug("id_pfr1: 0x%08x\n", id_pfr1);
203 /* Generic Timer Extension available? */
204 if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) {
205 uint32_t freq;
206
207 debug("Setting CNTFRQ\n");
208
209 /*
210 * CNTFRQ is a secure register, so we will crash if we try to
211 * write this from the non-secure world (read is OK, though).
212 * In case some bootcode has already set the correct value,
213 * we avoid the risk of writing to it.
214 */
215 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
216 if (freq != CONFIG_COUNTER_FREQUENCY) {
217 debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
218 freq, CONFIG_COUNTER_FREQUENCY);
219 #ifdef CONFIG_NON_SECURE
220 printf("arch timer frequency is wrong, but cannot adjust it\n");
221 #else
222 asm volatile("mcr p15, 0, %0, c14, c0, 0"
223 : : "r"(CONFIG_COUNTER_FREQUENCY));
224 #endif
225 }
226 }
227 #endif /* !CONFIG_ARM64 && !CONFIG_MACH_SUNIV */
228
229 ret = axp_gpio_init();
230 if (ret)
231 return ret;
232
233 eth_init_board();
234
235 return 0;
236 }
237
238 /*
239 * On older SoCs the SPL is actually at address zero, so using NULL as
240 * an error value does not work.
241 */
242 #define INVALID_SPL_HEADER ((void *)~0UL)
243
get_spl_header(uint8_t req_version)244 static struct boot_file_head * get_spl_header(uint8_t req_version)
245 {
246 struct boot_file_head *spl = (void *)(ulong)SPL_ADDR;
247 uint8_t spl_header_version = spl->spl_signature[3];
248
249 /* Is there really the SPL header (still) there? */
250 if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0)
251 return INVALID_SPL_HEADER;
252
253 if (spl_header_version < req_version) {
254 printf("sunxi SPL version mismatch: expected %u, got %u\n",
255 req_version, spl_header_version);
256 return INVALID_SPL_HEADER;
257 }
258
259 return spl;
260 }
261
get_spl_dt_name(void)262 static const char *get_spl_dt_name(void)
263 {
264 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
265
266 /* Check if there is a DT name stored in the SPL header. */
267 if (spl != INVALID_SPL_HEADER && spl->dt_name_offset)
268 return (char *)spl + spl->dt_name_offset;
269
270 return NULL;
271 }
272
dram_init(void)273 int dram_init(void)
274 {
275 struct boot_file_head *spl = get_spl_header(SPL_DRAM_HEADER_VERSION);
276
277 if (spl == INVALID_SPL_HEADER)
278 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0,
279 PHYS_SDRAM_0_SIZE);
280 else
281 gd->ram_size = (phys_addr_t)spl->dram_size << 20;
282
283 if (gd->ram_size > CONFIG_SUNXI_DRAM_MAX_SIZE)
284 gd->ram_size = CONFIG_SUNXI_DRAM_MAX_SIZE;
285
286 return 0;
287 }
288
289 #if defined(CONFIG_NAND_SUNXI) && defined(CONFIG_XPL_BUILD)
nand_pinmux_setup(void)290 static void nand_pinmux_setup(void)
291 {
292 unsigned int pin;
293
294 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++)
295 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
296
297 #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
298 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++)
299 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
300 #endif
301 /* sun4i / sun7i do have a PC23, but it is not used for nand,
302 * only sun7i has a PC24 */
303 #ifdef CONFIG_MACH_SUN7I
304 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
305 #endif
306 }
307
nand_clock_setup(void)308 static void nand_clock_setup(void)
309 {
310 struct sunxi_ccm_reg *const ccm =
311 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
312
313 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
314 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \
315 defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I
316 setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0));
317 #endif
318 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
319 }
320
board_nand_init(void)321 void board_nand_init(void)
322 {
323 nand_pinmux_setup();
324 nand_clock_setup();
325 }
326 #endif /* CONFIG_NAND_SUNXI */
327
328 #ifdef CONFIG_MMC
mmc_pinmux_setup(int sdc)329 static void mmc_pinmux_setup(int sdc)
330 {
331 unsigned int pin;
332
333 switch (sdc) {
334 case 0:
335 /* SDC0: PF0-PF5 */
336 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
337 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
338 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
339 sunxi_gpio_set_drv(pin, 2);
340 }
341 break;
342
343 case 1:
344 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
345 defined(CONFIG_MACH_SUN8I_R40)
346 if (IS_ENABLED(CONFIG_MMC1_PINS_PH)) {
347 /* SDC1: PH22-PH-27 */
348 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
349 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
350 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
351 sunxi_gpio_set_drv(pin, 2);
352 }
353 } else {
354 /* SDC1: PG0-PG5 */
355 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
356 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
357 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
358 sunxi_gpio_set_drv(pin, 2);
359 }
360 }
361 #elif defined(CONFIG_MACH_SUN5I)
362 /* SDC1: PG3-PG8 */
363 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
364 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
365 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
366 sunxi_gpio_set_drv(pin, 2);
367 }
368 #elif defined(CONFIG_MACH_SUN6I)
369 /* SDC1: PG0-PG5 */
370 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
371 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
372 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
373 sunxi_gpio_set_drv(pin, 2);
374 }
375 #elif defined(CONFIG_MACH_SUN8I)
376 /* SDC1: PG0-PG5 */
377 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
378 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
379 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
380 sunxi_gpio_set_drv(pin, 2);
381 }
382 #endif
383 break;
384
385 case 2:
386 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
387 /* SDC2: PC6-PC11 */
388 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
389 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
390 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
391 sunxi_gpio_set_drv(pin, 2);
392 }
393 #elif defined(CONFIG_MACH_SUN5I)
394 /* SDC2: PC6-PC15 */
395 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
396 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
397 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
398 sunxi_gpio_set_drv(pin, 2);
399 }
400 #elif defined(CONFIG_MACH_SUN6I)
401 /* SDC2: PC6-PC15, PC24 */
402 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
403 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
404 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
405 sunxi_gpio_set_drv(pin, 2);
406 }
407
408 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
409 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
410 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
411 #elif defined(CONFIG_MACH_SUN8I_R40)
412 /* SDC2: PC6-PC15, PC24 */
413 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
414 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
415 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
416 sunxi_gpio_set_drv(pin, 2);
417 }
418
419 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
420 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
421 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
422 #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
423 /* SDC2: PC5-PC6, PC8-PC16 */
424 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
425 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
426 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
427 sunxi_gpio_set_drv(pin, 2);
428 }
429
430 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
431 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
432 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
433 sunxi_gpio_set_drv(pin, 2);
434 }
435 #elif defined(CONFIG_MACH_SUN50I_H6)
436 /* SDC2: PC4-PC14 */
437 for (pin = SUNXI_GPC(4); pin <= SUNXI_GPC(14); pin++) {
438 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
439 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
440 sunxi_gpio_set_drv(pin, 2);
441 }
442 #elif defined(CONFIG_MACH_SUN50I_H616) || defined(CONFIG_MACH_SUN50I_A133) || \
443 defined(CONFIG_MACH_SUN55I_A523)
444 /* SDC2: PC0-PC1, PC5-PC6, PC8-PC11, PC13-PC16 */
445 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(16); pin++) {
446 if (pin > SUNXI_GPC(1) && pin < SUNXI_GPC(5))
447 continue;
448 if (pin == SUNXI_GPC(7) || pin == SUNXI_GPC(12))
449 continue;
450 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
451 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
452 sunxi_gpio_set_drv(pin, 3);
453 }
454 #elif defined(CONFIG_MACH_SUN9I)
455 /* SDC2: PC6-PC16 */
456 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
457 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
458 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
459 sunxi_gpio_set_drv(pin, 2);
460 }
461 #elif defined(CONFIG_MACH_SUN8I_R528)
462 /* SDC2: PC2-PC7 */
463 for (pin = SUNXI_GPC(2); pin <= SUNXI_GPC(7); pin++) {
464 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
465 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
466 sunxi_gpio_set_drv(pin, 2);
467 }
468 #else
469 puts("ERROR: No pinmux setup defined for MMC2!\n");
470 #endif
471 break;
472
473 case 3:
474 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
475 defined(CONFIG_MACH_SUN8I_R40)
476 /* SDC3: PI4-PI9 */
477 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
478 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
479 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
480 sunxi_gpio_set_drv(pin, 2);
481 }
482 #elif defined(CONFIG_MACH_SUN6I)
483 /* SDC3: PC6-PC15, PC24 */
484 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
485 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
486 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
487 sunxi_gpio_set_drv(pin, 2);
488 }
489
490 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
491 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
492 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
493 #endif
494 break;
495
496 default:
497 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
498 break;
499 }
500 }
501
board_mmc_init(struct bd_info * bis)502 int board_mmc_init(struct bd_info *bis)
503 {
504 /*
505 * The BROM always accesses MMC port 0 (typically an SD card), and
506 * most boards seem to have such a slot. The others haven't reported
507 * any problem with unconditionally enabling this in the SPL.
508 */
509 if (!IS_ENABLED(CONFIG_UART0_PORT_F)) {
510 mmc_pinmux_setup(0);
511 if (!sunxi_mmc_init(0))
512 return -1;
513 }
514
515 if (CONFIG_MMC_SUNXI_SLOT_EXTRA != -1) {
516 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
517 if (!sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA))
518 return -1;
519 }
520
521 return 0;
522 }
523
524 #ifdef CONFIG_ENV_MMC_DEVICE_INDEX
mmc_get_env_dev(void)525 int mmc_get_env_dev(void)
526 {
527 switch (sunxi_get_boot_device()) {
528 case BOOT_DEVICE_MMC1:
529 return 0;
530 case BOOT_DEVICE_MMC2:
531 return 1;
532 default:
533 return CONFIG_ENV_MMC_DEVICE_INDEX;
534 }
535 }
536 #endif
537 #endif /* CONFIG_MMC */
538
539 #ifdef CONFIG_XPL_BUILD
540
sunxi_spl_store_dram_size(phys_addr_t dram_size)541 static void sunxi_spl_store_dram_size(phys_addr_t dram_size)
542 {
543 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
544
545 if (spl == INVALID_SPL_HEADER)
546 return;
547
548 /* Promote the header version for U-Boot proper, if needed. */
549 if (spl->spl_signature[3] < SPL_DRAM_HEADER_VERSION)
550 spl->spl_signature[3] = SPL_DRAM_HEADER_VERSION;
551
552 spl->dram_size = dram_size >> 20;
553 }
554
sunxi_board_init(void)555 void sunxi_board_init(void)
556 {
557 int power_failed = 0;
558
559 #ifdef CONFIG_LED_STATUS
560 if (IS_ENABLED(CONFIG_SPL_DRIVERS_MISC))
561 status_led_init();
562 #endif
563
564 #ifdef CONFIG_SY8106A_POWER
565 power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
566 #endif
567
568 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
569 defined CONFIG_AXP221_POWER || defined CONFIG_AXP305_POWER || \
570 defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER || \
571 defined CONFIG_AXP313_POWER || defined CONFIG_AXP717_POWER || \
572 defined CONFIG_AXP803_POWER
573 power_failed = axp_init();
574
575 if (IS_ENABLED(CONFIG_AXP_DISABLE_BOOT_ON_POWERON) && !power_failed) {
576 u8 boot_reason;
577
578 pmic_bus_read(AXP_POWER_STATUS, &boot_reason);
579 if (boot_reason & AXP_POWER_STATUS_ALDO_IN) {
580 printf("Power on by plug-in, shutting down.\n");
581 pmic_bus_write(0x32, BIT(7));
582 }
583 }
584
585 #ifdef CONFIG_AXP_DCDC1_VOLT
586 power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
587 #endif
588 #ifdef CONFIG_AXP_DCDC2_VOLT
589 power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
590 #endif
591 #ifdef CONFIG_AXP_DCDC3_VOLT
592 power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
593 #endif
594 #ifdef CONFIG_AXP_DCDC4_VOLT
595 power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
596 #endif
597 #ifdef CONFIG_AXP_DCDC5_VOLT
598 power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
599 #endif
600
601 #ifdef CONFIG_AXP_ALDO1_VOLT
602 power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
603 #endif
604 #ifdef CONFIG_AXP_ALDO2_VOLT
605 power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
606 #endif
607 #ifdef CONFIG_AXP_ALDO3_VOLT
608 power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
609 #endif
610 #ifdef CONFIG_AXP_ALDO4_VOLT
611 power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
612 #endif
613
614 #ifdef CONFIG_AXP_DLDO1_VOLT
615 power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
616 power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
617 #endif
618 #ifdef CONFIG_AXP_DLDO3_VOLT
619 power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
620 power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
621 #endif
622 #ifdef CONFIG_AXP_ELDO1_VOLT
623 power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
624 power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
625 power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
626 #endif
627
628 #ifdef CONFIG_AXP_FLDO1_VOLT
629 power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
630 power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
631 power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
632 #endif
633
634 #if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
635 power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
636 #endif
637 #endif /* CONFIG_AXPxxx_POWER */
638 printf("DRAM:");
639 gd->ram_size = sunxi_dram_init();
640 printf(" %d MiB\n", (int)(gd->ram_size >> 20));
641 if (!gd->ram_size)
642 hang();
643
644 sunxi_spl_store_dram_size(gd->ram_size);
645
646 /*
647 * Only clock up the CPU to full speed if we are reasonably
648 * assured it's being powered with suitable core voltage
649 */
650 if (!power_failed)
651 clock_set_pll1(get_board_sys_clk());
652 else
653 printf("Failed to set core voltage! Can't set CPU frequency\n");
654 }
655 #endif /* CONFIG_XPL_BUILD */
656
657 #ifdef CONFIG_USB_GADGET
g_dnl_board_usb_cable_connected(void)658 int g_dnl_board_usb_cable_connected(void)
659 {
660 struct udevice *dev;
661 struct phy phy;
662 int ret;
663
664 ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev);
665 if (ret) {
666 pr_err("%s: Cannot find USB device\n", __func__);
667 return ret;
668 }
669
670 ret = generic_phy_get_by_name(dev, "usb", &phy);
671 if (ret) {
672 pr_err("failed to get %s USB PHY\n", dev->name);
673 return ret;
674 }
675
676 ret = generic_phy_init(&phy);
677 if (ret) {
678 pr_debug("failed to init %s USB PHY\n", dev->name);
679 return ret;
680 }
681
682 return sun4i_usb_phy_vbus_detect(&phy);
683 }
684 #endif /* CONFIG_USB_GADGET */
685
686 #ifdef CONFIG_SERIAL_TAG
get_board_serial(struct tag_serialnr * serialnr)687 void get_board_serial(struct tag_serialnr *serialnr)
688 {
689 char *serial_string;
690 unsigned long long serial;
691
692 serial_string = env_get("serial#");
693
694 if (serial_string) {
695 serial = simple_strtoull(serial_string, NULL, 16);
696
697 serialnr->high = (unsigned int) (serial >> 32);
698 serialnr->low = (unsigned int) (serial & 0xffffffff);
699 } else {
700 serialnr->high = 0;
701 serialnr->low = 0;
702 }
703 }
704 #endif
705
706 /*
707 * Check the SPL header for the "sunxi" variant. If found: parse values
708 * that might have been passed by the loader ("fel" utility), and update
709 * the environment accordingly.
710 */
parse_spl_header(const uint32_t spl_addr)711 static void parse_spl_header(const uint32_t spl_addr)
712 {
713 struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
714
715 if (spl == INVALID_SPL_HEADER)
716 return;
717
718 if (!spl->fel_script_address)
719 return;
720
721 if (spl->fel_uEnv_length != 0) {
722 /*
723 * data is expected in uEnv.txt compatible format, so "env
724 * import -t" the string(s) at fel_script_address right away.
725 */
726 himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address,
727 spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL);
728 return;
729 }
730 /* otherwise assume .scr format (mkimage-type script) */
731 env_set_hex("fel_scriptaddr", spl->fel_script_address);
732 }
733
get_unique_sid(unsigned int * sid)734 static bool get_unique_sid(unsigned int *sid)
735 {
736 if (sunxi_get_sid(sid) != 0)
737 return false;
738
739 if (!sid[0])
740 return false;
741
742 /*
743 * The single words 1 - 3 of the SID have quite a few bits
744 * which are the same on many models, so we take a crc32
745 * of all 3 words, to get a more unique value.
746 *
747 * Note we only do this on newer SoCs as we cannot change
748 * the algorithm on older SoCs since those have been using
749 * fixed mac-addresses based on only using word 3 for a
750 * long time and changing a fixed mac-address with an
751 * u-boot update is not good.
752 */
753 #if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
754 !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
755 !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
756 sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
757 #endif
758
759 /* Ensure the NIC specific bytes of the mac are not all 0 */
760 if ((sid[3] & 0xffffff) == 0)
761 sid[3] |= 0x800000;
762
763 return true;
764 }
765
766 /*
767 * Note this function gets called multiple times.
768 * It must not make any changes to env variables which already exist.
769 */
setup_environment(const void * fdt)770 static void setup_environment(const void *fdt)
771 {
772 char serial_string[17] = { 0 };
773 unsigned int sid[4];
774 uint8_t mac_addr[6];
775 char ethaddr[16];
776 int i;
777
778 if (!get_unique_sid(sid))
779 return;
780
781 for (i = 0; i < 4; i++) {
782 sprintf(ethaddr, "ethernet%d", i);
783 if (!fdt_get_alias(fdt, ethaddr))
784 continue;
785
786 if (i == 0)
787 strcpy(ethaddr, "ethaddr");
788 else
789 sprintf(ethaddr, "eth%daddr", i);
790
791 if (env_get(ethaddr))
792 continue;
793
794 /* Non OUI / registered MAC address */
795 mac_addr[0] = (i << 4) | 0x02;
796 mac_addr[1] = (sid[0] >> 0) & 0xff;
797 mac_addr[2] = (sid[3] >> 24) & 0xff;
798 mac_addr[3] = (sid[3] >> 16) & 0xff;
799 mac_addr[4] = (sid[3] >> 8) & 0xff;
800 mac_addr[5] = (sid[3] >> 0) & 0xff;
801
802 eth_env_set_enetaddr(ethaddr, mac_addr);
803 }
804
805 if (!env_get("serial#")) {
806 snprintf(serial_string, sizeof(serial_string),
807 "%08x%08x", sid[0], sid[3]);
808
809 env_set("serial#", serial_string);
810 }
811 }
812
misc_init_r(void)813 int misc_init_r(void)
814 {
815 const char *spl_dt_name;
816 uint boot;
817
818 env_set("fel_booted", NULL);
819 env_set("fel_scriptaddr", NULL);
820 env_set("mmc_bootdev", NULL);
821
822 boot = sunxi_get_boot_device();
823 /* determine if we are running in FEL mode */
824 if (boot == BOOT_DEVICE_BOARD) {
825 env_set("fel_booted", "1");
826 parse_spl_header(SPL_ADDR);
827 /* or if we booted from MMC, and which one */
828 } else if (boot == BOOT_DEVICE_MMC1) {
829 env_set("mmc_bootdev", "0");
830 } else if (boot == BOOT_DEVICE_MMC2) {
831 env_set("mmc_bootdev", "1");
832 }
833
834 /* Set fdtfile to match the FIT configuration chosen in SPL. */
835 spl_dt_name = get_spl_dt_name();
836 if (spl_dt_name) {
837 char *prefix = IS_ENABLED(CONFIG_ARM64) ? "allwinner/" : "";
838 char str[64];
839
840 snprintf(str, sizeof(str), "%s%s.dtb", prefix, spl_dt_name);
841 env_set("fdtfile", str);
842 }
843
844 setup_environment(gd->fdt_blob);
845
846 return 0;
847 }
848
board_late_init(void)849 int board_late_init(void)
850 {
851 #ifdef CONFIG_USB_ETHER
852 usb_ether_init();
853 #endif
854
855 return 0;
856 }
857
bluetooth_dt_fixup(void * blob)858 static void bluetooth_dt_fixup(void *blob)
859 {
860 /* Some devices ship with a Bluetooth controller default address.
861 * Set a valid address through the device tree.
862 */
863 uchar tmp[ETH_ALEN], bdaddr[ETH_ALEN];
864 unsigned int sid[4];
865 int i;
866
867 if (!CONFIG_BLUETOOTH_DT_DEVICE_FIXUP[0])
868 return;
869
870 if (eth_env_get_enetaddr("bdaddr", tmp)) {
871 /* Convert between the binary formats of the corresponding stacks */
872 for (i = 0; i < ETH_ALEN; ++i)
873 bdaddr[i] = tmp[ETH_ALEN - i - 1];
874 } else {
875 if (!get_unique_sid(sid))
876 return;
877
878 bdaddr[0] = ((sid[3] >> 0) & 0xff) ^ 1;
879 bdaddr[1] = (sid[3] >> 8) & 0xff;
880 bdaddr[2] = (sid[3] >> 16) & 0xff;
881 bdaddr[3] = (sid[3] >> 24) & 0xff;
882 bdaddr[4] = (sid[0] >> 0) & 0xff;
883 bdaddr[5] = 0x02;
884 }
885
886 do_fixup_by_compat(blob, CONFIG_BLUETOOTH_DT_DEVICE_FIXUP,
887 "local-bd-address", bdaddr, ETH_ALEN, 1);
888 }
889
890 #define PINEPHONE_LIS3MDL_I2C_ADDR 0x1e
891 #define PINEPHONE_LIS3MDL_I2C_BUS 1 /* I2C1 */
892
board_dt_fixup(void * blob)893 static void board_dt_fixup(void *blob)
894 {
895 struct udevice *bus, *dev;
896
897 if (IS_ENABLED(CONFIG_PINEPHONE_DT_SELECTION) &&
898 !fdt_node_check_compatible(blob, 0, "pine64,pinephone-1.2")) {
899 if (!uclass_get_device_by_seq(UCLASS_I2C,
900 PINEPHONE_LIS3MDL_I2C_BUS,
901 &bus)) {
902 dm_i2c_probe(bus, PINEPHONE_LIS3MDL_I2C_ADDR, 0, &dev);
903 fdt_set_status_by_compatible(blob, "st,lis3mdl-magn",
904 dev ? FDT_STATUS_OKAY : FDT_STATUS_DISABLED);
905 fdt_set_status_by_compatible(blob, "voltafield,af8133j",
906 dev ? FDT_STATUS_DISABLED : FDT_STATUS_OKAY);
907 }
908 }
909 }
910
ft_board_setup(void * blob,struct bd_info * bd)911 int ft_board_setup(void *blob, struct bd_info *bd)
912 {
913 int __maybe_unused r;
914
915 /*
916 * Call setup_environment and fdt_fixup_ethernet again
917 * in case the boot fdt has ethernet aliases the u-boot
918 * copy does not have.
919 */
920 setup_environment(blob);
921 fdt_fixup_ethernet(blob);
922
923 bluetooth_dt_fixup(blob);
924 board_dt_fixup(blob);
925
926 #ifdef CONFIG_VIDEO_DT_SIMPLEFB
927 r = sunxi_simplefb_setup(blob);
928 if (r)
929 return r;
930 #endif
931 return 0;
932 }
933
934 #ifdef CONFIG_SPL_LOAD_FIT
set_spl_dt_name(const char * name)935 static void set_spl_dt_name(const char *name)
936 {
937 struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
938
939 if (spl == INVALID_SPL_HEADER)
940 return;
941
942 /* Promote the header version for U-Boot proper, if needed. */
943 if (spl->spl_signature[3] < SPL_DT_HEADER_VERSION)
944 spl->spl_signature[3] = SPL_DT_HEADER_VERSION;
945
946 strcpy((char *)&spl->string_pool, name);
947 spl->dt_name_offset = offsetof(struct boot_file_head, string_pool);
948 }
949
board_fit_config_name_match(const char * name)950 int board_fit_config_name_match(const char *name)
951 {
952 const char *best_dt_name = get_spl_dt_name();
953 int ret;
954
955 #ifdef CONFIG_DEFAULT_DEVICE_TREE
956 if (best_dt_name == NULL)
957 best_dt_name = CONFIG_DEFAULT_DEVICE_TREE;
958 #endif
959
960 if (best_dt_name == NULL) {
961 /* No DT name was provided, so accept the first config. */
962 return 0;
963 }
964 #ifdef CONFIG_PINE64_DT_SELECTION
965 if (strstr(best_dt_name, "-pine64-plus")) {
966 /* Differentiate the Pine A64 boards by their DRAM size. */
967 if (gd->ram_size == SZ_512M)
968 best_dt_name = "sun50i-a64-pine64";
969 }
970 #endif
971 #ifdef CONFIG_PINEPHONE_DT_SELECTION
972 if (strstr(best_dt_name, "-pinephone")) {
973 /* Differentiate the PinePhone revisions by GPIO inputs. */
974 prcm_apb0_enable(PRCM_APB0_GATE_PIO);
975 sunxi_gpio_set_pull(SUNXI_GPL(6), SUNXI_GPIO_PULL_UP);
976 sunxi_gpio_set_cfgpin(SUNXI_GPL(6), SUNXI_GPIO_INPUT);
977 udelay(100);
978
979 /* PL6 is pulled low by the modem on v1.2. */
980 if (gpio_get_value(SUNXI_GPL(6)) == 0)
981 best_dt_name = "sun50i-a64-pinephone-1.2";
982 else
983 best_dt_name = "sun50i-a64-pinephone-1.1";
984
985 sunxi_gpio_set_cfgpin(SUNXI_GPL(6), SUNXI_GPIO_DISABLE);
986 sunxi_gpio_set_pull(SUNXI_GPL(6), SUNXI_GPIO_PULL_DISABLE);
987 prcm_apb0_disable(PRCM_APB0_GATE_PIO);
988 }
989 #endif
990
991 ret = strcmp(name, best_dt_name);
992
993 /*
994 * If one of the FIT configurations matches the most accurate DT name,
995 * update the SPL header to provide that DT name to U-Boot proper.
996 */
997 if (ret == 0)
998 set_spl_dt_name(best_dt_name);
999
1000 return ret;
1001 }
1002 #endif /* CONFIG_SPL_LOAD_FIT */
1003