1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Board specific initialization for AM642 EVM
4  *
5  * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
6  *	Keerthy <j-keerthy@ti.com>
7  *
8  */
9 
10 #include <efi_loader.h>
11 #include <asm/io.h>
12 #include <dm/uclass.h>
13 #include <k3-ddrss.h>
14 #include <spl.h>
15 #include <fdt_support.h>
16 #include <asm/arch/hardware.h>
17 #include <env.h>
18 #include <asm/arch/k3-ddr.h>
19 
20 #include "../common/board_detect.h"
21 #include "../common/fdt_ops.h"
22 
23 #define board_is_am64x_gpevm() (board_ti_k3_is("AM64-GPEVM") || \
24 				board_ti_k3_is("AM64-EVM") || \
25 				board_ti_k3_is("AM64-HSEVM"))
26 
27 #define board_is_am64x_skevm() (board_ti_k3_is("AM64-SKEVM") || \
28 				board_ti_k3_is("AM64B-SKEVM"))
29 
30 DECLARE_GLOBAL_DATA_PTR;
31 
32 struct efi_fw_image fw_images[] = {
33 	{
34 		.image_type_id = AM64X_SK_TIBOOT3_IMAGE_GUID,
35 		.fw_name = u"AM64X_SK_TIBOOT3",
36 		.image_index = 1,
37 	},
38 	{
39 		.image_type_id = AM64X_SK_SPL_IMAGE_GUID,
40 		.fw_name = u"AM64X_SK_SPL",
41 		.image_index = 2,
42 	},
43 	{
44 		.image_type_id = AM64X_SK_UBOOT_IMAGE_GUID,
45 		.fw_name = u"AM64X_SK_UBOOT",
46 		.image_index = 3,
47 	}
48 };
49 
50 struct efi_capsule_update_info update_info = {
51 	.dfu_string = "sf 0:0=tiboot3.bin raw 0 100000;"
52 	"tispl.bin raw 100000 200000;u-boot.img raw 300000 400000",
53 	.num_images = ARRAY_SIZE(fw_images),
54 	.images = fw_images,
55 };
56 
57 #if defined(CONFIG_SPL_LOAD_FIT)
board_fit_config_name_match(const char * name)58 int board_fit_config_name_match(const char *name)
59 {
60 	bool eeprom_read = board_ti_was_eeprom_read();
61 
62 	if (!eeprom_read || board_is_am64x_gpevm()) {
63 		if (!strcmp(name, "k3-am642-r5-evm") || !strcmp(name, "k3-am642-evm"))
64 			return 0;
65 	} else if (board_is_am64x_skevm()) {
66 		if (!strcmp(name, "k3-am642-r5-sk") || !strcmp(name, "k3-am642-sk"))
67 			return 0;
68 	}
69 
70 	return -1;
71 }
72 #endif
73 
74 #if defined(CONFIG_XPL_BUILD)
75 #if CONFIG_IS_ENABLED(USB_STORAGE)
fixup_usb_boot(const void * fdt_blob)76 static int fixup_usb_boot(const void *fdt_blob)
77 {
78 	int ret = 0;
79 
80 	switch (spl_boot_device()) {
81 	case BOOT_DEVICE_USB:
82 		/*
83 		 * If the boot mode is host, fixup the dr_mode to host
84 		 * before cdns3 bind takes place
85 		 */
86 		ret = fdt_find_and_setprop((void *)fdt_blob,
87 					   "/bus@f4000/cdns-usb@f900000/usb@f400000",
88 					   "dr_mode", "host", 5, 0);
89 		if (ret)
90 			printf("%s: fdt_find_and_setprop() failed:%d\n",
91 			       __func__, ret);
92 		fallthrough;
93 	default:
94 		break;
95 	}
96 
97 	return ret;
98 }
99 #endif
100 
spl_perform_fixups(struct spl_image_info * spl_image)101 void spl_perform_fixups(struct spl_image_info *spl_image)
102 {
103 	if (IS_ENABLED(CONFIG_K3_DDRSS)) {
104 		if (IS_ENABLED(CONFIG_K3_INLINE_ECC))
105 			fixup_ddr_driver_for_ecc(spl_image);
106 	} else {
107 		fixup_memory_node(spl_image);
108 	}
109 
110 #if CONFIG_IS_ENABLED(USB_STORAGE)
111 	fixup_usb_boot(spl_image->fdt_addr);
112 #endif
113 }
114 #endif
115 
116 #ifdef CONFIG_TI_I2C_BOARD_DETECT
do_board_detect(void)117 int do_board_detect(void)
118 {
119 	int ret;
120 
121 	ret = ti_i2c_eeprom_am6_get_base(CONFIG_EEPROM_BUS_ADDRESS,
122 					 CONFIG_EEPROM_CHIP_ADDRESS);
123 	if (ret) {
124 		printf("EEPROM not available at 0x%02x, trying to read at 0x%02x\n",
125 			CONFIG_EEPROM_CHIP_ADDRESS, CONFIG_EEPROM_CHIP_ADDRESS + 1);
126 		ret = ti_i2c_eeprom_am6_get_base(CONFIG_EEPROM_BUS_ADDRESS,
127 						 CONFIG_EEPROM_CHIP_ADDRESS + 1);
128 		if (ret)
129 			pr_err("Reading on-board EEPROM at 0x%02x failed %d\n",
130 			       CONFIG_EEPROM_CHIP_ADDRESS + 1, ret);
131 	}
132 
133 	return ret;
134 }
135 
checkboard(void)136 int checkboard(void)
137 {
138 	struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA;
139 
140 	if (!do_board_detect())
141 		printf("Board: %s rev %s\n", ep->name, ep->version);
142 
143 	return 0;
144 }
145 
146 #ifdef CONFIG_BOARD_LATE_INIT
147 static struct ti_fdt_map ti_am64_evm_fdt_map[] = {
148 	{"am64x_gpevm", "ti/k3-am642-evm.dtb"},
149 	{"am64x_skevm", "ti/k3-am642-sk.dtb"},
150 	{ /* Sentinel. */ }
151 };
152 
setup_board_eeprom_env(void)153 static void setup_board_eeprom_env(void)
154 {
155 	char *name = "am64x_gpevm";
156 
157 	if (do_board_detect())
158 		goto invalid_eeprom;
159 
160 	if (board_is_am64x_gpevm())
161 		name = "am64x_gpevm";
162 	else if (board_is_am64x_skevm())
163 		name = "am64x_skevm";
164 	else
165 		printf("Unidentified board claims %s in eeprom header\n",
166 		       board_ti_get_name());
167 
168 invalid_eeprom:
169 	set_board_info_env_am6(name);
170 	ti_set_fdt_env(name, ti_am64_evm_fdt_map);
171 }
172 
setup_serial(void)173 static void setup_serial(void)
174 {
175 	struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA;
176 	unsigned long board_serial;
177 	char *endp;
178 	char serial_string[17] = { 0 };
179 
180 	if (env_get("serial#"))
181 		return;
182 
183 	board_serial = hextoul(ep->serial, &endp);
184 	if (*endp != '\0') {
185 		pr_err("Error: Can't set serial# to %s\n", ep->serial);
186 		return;
187 	}
188 
189 	snprintf(serial_string, sizeof(serial_string), "%016lx", board_serial);
190 	env_set("serial#", serial_string);
191 }
192 #endif
193 #endif
194 
195 #ifdef CONFIG_BOARD_LATE_INIT
board_late_init(void)196 int board_late_init(void)
197 {
198 	if (IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT)) {
199 		struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA;
200 
201 		setup_board_eeprom_env();
202 		setup_serial();
203 		/*
204 		 * The first MAC address for ethernet a.k.a. ethernet0 comes from
205 		 * efuse populated via the am654 gigabit eth switch subsystem driver.
206 		 * All the other ones are populated via EEPROM, hence continue with
207 		 * an index of 1.
208 		 */
209 		board_ti_am6_set_ethaddr(1, ep->mac_addr_cnt);
210 	}
211 
212 	return 0;
213 }
214 #endif
215 
216 #define CTRLMMR_USB0_PHY_CTRL	0x43004008
217 #define CORE_VOLTAGE		0x80000000
218 
219 #ifdef CONFIG_SPL_BOARD_INIT
spl_board_init(void)220 void spl_board_init(void)
221 {
222 	u32 val;
223 	/* Set USB PHY core voltage to 0.85V */
224 	val = readl(CTRLMMR_USB0_PHY_CTRL);
225 	val &= ~(CORE_VOLTAGE);
226 	writel(val, CTRLMMR_USB0_PHY_CTRL);
227 
228 	/* Init DRAM size for R5/A53 SPL */
229 	dram_init_banksize();
230 }
231 #endif
232