1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2013
4 * Texas Instruments Incorporated, <www.ti.com>
5 *
6 * Lokesh Vutla <lokeshvutla@ti.com>
7 *
8 * Based on previous work by:
9 * Aneesh V <aneesh@ti.com>
10 * Steve Sakoman <steve@sakoman.com>
11 */
12 #include <config.h>
13 #include <env.h>
14 #include <fdt_support.h>
15 #include <fastboot.h>
16 #include <init.h>
17 #include <spl.h>
18 #include <net.h>
19 #include <palmas.h>
20 #include <sata.h>
21 #include <serial.h>
22 #include <asm/global_data.h>
23 #include <linux/string.h>
24 #include <asm/gpio.h>
25 #include <usb.h>
26 #include <linux/usb/gadget.h>
27 #include <asm/omap_common.h>
28 #include <asm/arch/gpio.h>
29 #include <asm/arch/dra7xx_iodelay.h>
30 #include <asm/emif.h>
31 #include <asm/arch/sys_proto.h>
32 #include <asm/arch/mmc_host_def.h>
33 #include <asm/arch/sata.h>
34 #include <dwc3-uboot.h>
35 #include <dwc3-omap-uboot.h>
36 #include <i2c.h>
37 #include <ti-usb-phy-uboot.h>
38
39 #include "mux_data.h"
40 #include "../common/board_detect.h"
41
42 #define board_is_dra76x_evm() board_ti_is("DRA76/7x")
43 #define board_is_dra74x_evm() board_ti_is("5777xCPU")
44 #define board_is_dra72x_evm() board_ti_is("DRA72x-T")
45 #define board_is_dra71x_evm() board_ti_is("DRA79x,D")
46 #define board_is_dra74x_revh_or_later() (board_is_dra74x_evm() && \
47 (strncmp("H", board_ti_get_rev(), 1) <= 0))
48 #define board_is_dra72x_revc_or_later() (board_is_dra72x_evm() && \
49 (strncmp("C", board_ti_get_rev(), 1) <= 0))
50 #define board_ti_get_emif_size() board_ti_get_emif1_size() + \
51 board_ti_get_emif2_size()
52
53 DECLARE_GLOBAL_DATA_PTR;
54
55 /* GPIO 7_11 */
56 #define GPIO_DDR_VTT_EN 203
57
58 #define SYSINFO_BOARD_NAME_MAX_LEN 37
59
60 /* I2C I/O Expander */
61 #define NAND_PCF8575_ADDR 0x21
62 #define NAND_PCF8575_I2C_BUS_NUM 0
63
64 const struct omap_sysinfo sysinfo = {
65 "Board: UNKNOWN(DRA7 EVM) REV UNKNOWN\n"
66 };
67
68 static const struct emif_regs emif1_ddr3_532_mhz_1cs = {
69 .sdram_config_init = 0x61851ab2,
70 .sdram_config = 0x61851ab2,
71 .sdram_config2 = 0x08000000,
72 .ref_ctrl = 0x000040F1,
73 .ref_ctrl_final = 0x00001035,
74 .sdram_tim1 = 0xCCCF36B3,
75 .sdram_tim2 = 0x308F7FDA,
76 .sdram_tim3 = 0x427F88A8,
77 .read_idle_ctrl = 0x00050000,
78 .zq_config = 0x0007190B,
79 .temp_alert_config = 0x00000000,
80 .emif_ddr_phy_ctlr_1_init = 0x0024400B,
81 .emif_ddr_phy_ctlr_1 = 0x0E24400B,
82 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
83 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
84 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
85 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
86 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
87 .emif_rd_wr_lvl_rmp_win = 0x00000000,
88 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
89 .emif_rd_wr_lvl_ctl = 0x00000000,
90 .emif_rd_wr_exec_thresh = 0x00000305
91 };
92
93 static const struct emif_regs emif2_ddr3_532_mhz_1cs = {
94 .sdram_config_init = 0x61851B32,
95 .sdram_config = 0x61851B32,
96 .sdram_config2 = 0x08000000,
97 .ref_ctrl = 0x000040F1,
98 .ref_ctrl_final = 0x00001035,
99 .sdram_tim1 = 0xCCCF36B3,
100 .sdram_tim2 = 0x308F7FDA,
101 .sdram_tim3 = 0x427F88A8,
102 .read_idle_ctrl = 0x00050000,
103 .zq_config = 0x0007190B,
104 .temp_alert_config = 0x00000000,
105 .emif_ddr_phy_ctlr_1_init = 0x0024400B,
106 .emif_ddr_phy_ctlr_1 = 0x0E24400B,
107 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
108 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
109 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
110 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
111 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
112 .emif_rd_wr_lvl_rmp_win = 0x00000000,
113 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
114 .emif_rd_wr_lvl_ctl = 0x00000000,
115 .emif_rd_wr_exec_thresh = 0x00000305
116 };
117
118 static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
119 .sdram_config_init = 0x61862B32,
120 .sdram_config = 0x61862B32,
121 .sdram_config2 = 0x08000000,
122 .ref_ctrl = 0x0000514C,
123 .ref_ctrl_final = 0x0000144A,
124 .sdram_tim1 = 0xD113781C,
125 .sdram_tim2 = 0x30717FE3,
126 .sdram_tim3 = 0x409F86A8,
127 .read_idle_ctrl = 0x00050000,
128 .zq_config = 0x5007190B,
129 .temp_alert_config = 0x00000000,
130 .emif_ddr_phy_ctlr_1_init = 0x0024400D,
131 .emif_ddr_phy_ctlr_1 = 0x0E24400D,
132 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
133 .emif_ddr_ext_phy_ctrl_2 = 0x00A400A4,
134 .emif_ddr_ext_phy_ctrl_3 = 0x00A900A9,
135 .emif_ddr_ext_phy_ctrl_4 = 0x00B000B0,
136 .emif_ddr_ext_phy_ctrl_5 = 0x00B000B0,
137 .emif_rd_wr_lvl_rmp_win = 0x00000000,
138 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
139 .emif_rd_wr_lvl_ctl = 0x00000000,
140 .emif_rd_wr_exec_thresh = 0x00000305
141 };
142
143 const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es2 = {
144 .sdram_config_init = 0x61862BB2,
145 .sdram_config = 0x61862BB2,
146 .sdram_config2 = 0x00000000,
147 .ref_ctrl = 0x0000514D,
148 .ref_ctrl_final = 0x0000144A,
149 .sdram_tim1 = 0xD1137824,
150 .sdram_tim2 = 0x30B37FE3,
151 .sdram_tim3 = 0x409F8AD8,
152 .read_idle_ctrl = 0x00050000,
153 .zq_config = 0x5007190B,
154 .temp_alert_config = 0x00000000,
155 .emif_ddr_phy_ctlr_1_init = 0x0824400E,
156 .emif_ddr_phy_ctlr_1 = 0x0E24400E,
157 .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
158 .emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
159 .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
160 .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
161 .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
162 .emif_rd_wr_lvl_rmp_win = 0x00000000,
163 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
164 .emif_rd_wr_lvl_ctl = 0x00000000,
165 .emif_rd_wr_exec_thresh = 0x00000305
166 };
167
168 const struct emif_regs emif1_ddr3_532_mhz_1cs_2G = {
169 .sdram_config_init = 0x61851ab2,
170 .sdram_config = 0x61851ab2,
171 .sdram_config2 = 0x08000000,
172 .ref_ctrl = 0x000040F1,
173 .ref_ctrl_final = 0x00001035,
174 .sdram_tim1 = 0xCCCF36B3,
175 .sdram_tim2 = 0x30BF7FDA,
176 .sdram_tim3 = 0x427F8BA8,
177 .read_idle_ctrl = 0x00050000,
178 .zq_config = 0x0007190B,
179 .temp_alert_config = 0x00000000,
180 .emif_ddr_phy_ctlr_1_init = 0x0024400B,
181 .emif_ddr_phy_ctlr_1 = 0x0E24400B,
182 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
183 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
184 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
185 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
186 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
187 .emif_rd_wr_lvl_rmp_win = 0x00000000,
188 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
189 .emif_rd_wr_lvl_ctl = 0x00000000,
190 .emif_rd_wr_exec_thresh = 0x00000305
191 };
192
193 const struct emif_regs emif2_ddr3_532_mhz_1cs_2G = {
194 .sdram_config_init = 0x61851B32,
195 .sdram_config = 0x61851B32,
196 .sdram_config2 = 0x08000000,
197 .ref_ctrl = 0x000040F1,
198 .ref_ctrl_final = 0x00001035,
199 .sdram_tim1 = 0xCCCF36B3,
200 .sdram_tim2 = 0x308F7FDA,
201 .sdram_tim3 = 0x427F88A8,
202 .read_idle_ctrl = 0x00050000,
203 .zq_config = 0x0007190B,
204 .temp_alert_config = 0x00000000,
205 .emif_ddr_phy_ctlr_1_init = 0x0024400B,
206 .emif_ddr_phy_ctlr_1 = 0x0E24400B,
207 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
208 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
209 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
210 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
211 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
212 .emif_rd_wr_lvl_rmp_win = 0x00000000,
213 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
214 .emif_rd_wr_lvl_ctl = 0x00000000,
215 .emif_rd_wr_exec_thresh = 0x00000305
216 };
217
218 const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra76 = {
219 .sdram_config_init = 0x61862B32,
220 .sdram_config = 0x61862B32,
221 .sdram_config2 = 0x00000000,
222 .ref_ctrl = 0x0000514C,
223 .ref_ctrl_final = 0x0000144A,
224 .sdram_tim1 = 0xD113783C,
225 .sdram_tim2 = 0x30B47FE3,
226 .sdram_tim3 = 0x409F8AD8,
227 .read_idle_ctrl = 0x00050000,
228 .zq_config = 0x5007190B,
229 .temp_alert_config = 0x00000000,
230 .emif_ddr_phy_ctlr_1_init = 0x0824400D,
231 .emif_ddr_phy_ctlr_1 = 0x0E24400D,
232 .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
233 .emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
234 .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
235 .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
236 .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
237 .emif_rd_wr_lvl_rmp_win = 0x00000000,
238 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
239 .emif_rd_wr_lvl_ctl = 0x00000000,
240 .emif_rd_wr_exec_thresh = 0x00000305
241 };
242
243 const struct emif_regs emif_2_regs_ddr3_666_mhz_1cs_dra76 = {
244 .sdram_config_init = 0x61862B32,
245 .sdram_config = 0x61862B32,
246 .sdram_config2 = 0x00000000,
247 .ref_ctrl = 0x0000514C,
248 .ref_ctrl_final = 0x0000144A,
249 .sdram_tim1 = 0xD113781C,
250 .sdram_tim2 = 0x30B47FE3,
251 .sdram_tim3 = 0x409F8AD8,
252 .read_idle_ctrl = 0x00050000,
253 .zq_config = 0x5007190B,
254 .temp_alert_config = 0x00000000,
255 .emif_ddr_phy_ctlr_1_init = 0x0824400D,
256 .emif_ddr_phy_ctlr_1 = 0x0E24400D,
257 .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
258 .emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
259 .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
260 .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
261 .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
262 .emif_rd_wr_lvl_rmp_win = 0x00000000,
263 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
264 .emif_rd_wr_lvl_ctl = 0x00000000,
265 .emif_rd_wr_exec_thresh = 0x00000305
266 };
267
emif_get_reg_dump(u32 emif_nr,const struct emif_regs ** regs)268 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
269 {
270 u64 ram_size;
271
272 ram_size = board_ti_get_emif_size();
273
274 switch (omap_revision()) {
275 case DRA752_ES1_0:
276 case DRA752_ES1_1:
277 case DRA752_ES2_0:
278 switch (emif_nr) {
279 case 1:
280 if (ram_size > CFG_MAX_MEM_MAPPED)
281 *regs = &emif1_ddr3_532_mhz_1cs_2G;
282 else
283 *regs = &emif1_ddr3_532_mhz_1cs;
284 break;
285 case 2:
286 if (ram_size > CFG_MAX_MEM_MAPPED)
287 *regs = &emif2_ddr3_532_mhz_1cs_2G;
288 else
289 *regs = &emif2_ddr3_532_mhz_1cs;
290 break;
291 }
292 break;
293 case DRA762_ABZ_ES1_0:
294 case DRA762_ACD_ES1_0:
295 case DRA762_ES1_0:
296 if (emif_nr == 1)
297 *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra76;
298 else
299 *regs = &emif_2_regs_ddr3_666_mhz_1cs_dra76;
300 break;
301 case DRA722_ES1_0:
302 case DRA722_ES2_0:
303 case DRA722_ES2_1:
304 if (ram_size < CFG_MAX_MEM_MAPPED)
305 *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
306 else
307 *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es2;
308 break;
309 default:
310 *regs = &emif1_ddr3_532_mhz_1cs;
311 }
312 }
313
314 static const struct dmm_lisa_map_regs lisa_map_dra7_1536MB = {
315 .dmm_lisa_map_0 = 0x0,
316 .dmm_lisa_map_1 = 0x80640300,
317 .dmm_lisa_map_2 = 0xC0500220,
318 .dmm_lisa_map_3 = 0xFF020100,
319 .is_ma_present = 0x1
320 };
321
322 static const struct dmm_lisa_map_regs lisa_map_2G_x_2 = {
323 .dmm_lisa_map_0 = 0x0,
324 .dmm_lisa_map_1 = 0x0,
325 .dmm_lisa_map_2 = 0x80600100,
326 .dmm_lisa_map_3 = 0xFF020100,
327 .is_ma_present = 0x1
328 };
329
330 const struct dmm_lisa_map_regs lisa_map_dra7_2GB = {
331 .dmm_lisa_map_0 = 0x0,
332 .dmm_lisa_map_1 = 0x0,
333 .dmm_lisa_map_2 = 0x80740300,
334 .dmm_lisa_map_3 = 0xFF020100,
335 .is_ma_present = 0x1
336 };
337
338 /*
339 * DRA722 EVM EMIF1 2GB CONFIGURATION
340 * EMIF1 4 devices of 512Mb x 8 Micron
341 */
342 const struct dmm_lisa_map_regs lisa_map_2G_x_4 = {
343 .dmm_lisa_map_0 = 0x0,
344 .dmm_lisa_map_1 = 0x0,
345 .dmm_lisa_map_2 = 0x80700100,
346 .dmm_lisa_map_3 = 0xFF020100,
347 .is_ma_present = 0x1
348 };
349
emif_get_dmm_regs(const struct dmm_lisa_map_regs ** dmm_lisa_regs)350 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
351 {
352 u64 ram_size;
353
354 ram_size = board_ti_get_emif_size();
355
356 switch (omap_revision()) {
357 case DRA762_ABZ_ES1_0:
358 case DRA762_ACD_ES1_0:
359 case DRA762_ES1_0:
360 case DRA752_ES1_0:
361 case DRA752_ES1_1:
362 case DRA752_ES2_0:
363 if (ram_size > CFG_MAX_MEM_MAPPED)
364 *dmm_lisa_regs = &lisa_map_dra7_2GB;
365 else
366 *dmm_lisa_regs = &lisa_map_dra7_1536MB;
367 break;
368 case DRA722_ES1_0:
369 case DRA722_ES2_0:
370 case DRA722_ES2_1:
371 default:
372 if (ram_size < CFG_MAX_MEM_MAPPED)
373 *dmm_lisa_regs = &lisa_map_2G_x_2;
374 else
375 *dmm_lisa_regs = &lisa_map_2G_x_4;
376 break;
377 }
378 }
379
380 struct vcores_data dra752_volts = {
381 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
382 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
383 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
384 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
385 .mpu.pmic = &tps659038,
386 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
387
388 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
389 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
390 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
391 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
392 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
393 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
394 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
395 .eve.addr = TPS659038_REG_ADDR_SMPS45,
396 .eve.pmic = &tps659038,
397 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
398
399 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
400 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
401 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
402 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
403 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
404 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
405 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
406 .gpu.addr = TPS659038_REG_ADDR_SMPS6,
407 .gpu.pmic = &tps659038,
408 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
409
410 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
411 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
412 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
413 .core.addr = TPS659038_REG_ADDR_SMPS7,
414 .core.pmic = &tps659038,
415
416 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
417 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
418 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
419 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
420 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
421 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
422 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
423 .iva.addr = TPS659038_REG_ADDR_SMPS8,
424 .iva.pmic = &tps659038,
425 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
426 };
427
428 struct vcores_data dra76x_volts = {
429 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
430 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
431 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
432 .mpu.addr = LP87565_REG_ADDR_BUCK01,
433 .mpu.pmic = &lp87565,
434 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
435
436 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
437 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
438 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
439 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
440 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
441 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
442 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
443 .eve.addr = TPS65917_REG_ADDR_SMPS1,
444 .eve.pmic = &tps659038,
445 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
446
447 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
448 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
449 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
450 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
451 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
452 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
453 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
454 .gpu.addr = LP87565_REG_ADDR_BUCK23,
455 .gpu.pmic = &lp87565,
456 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
457
458 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
459 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
460 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
461 .core.addr = TPS65917_REG_ADDR_SMPS3,
462 .core.pmic = &tps659038,
463
464 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
465 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
466 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
467 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
468 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
469 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
470 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
471 .iva.addr = TPS65917_REG_ADDR_SMPS4,
472 .iva.pmic = &tps659038,
473 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
474 };
475
476 struct vcores_data dra722_volts = {
477 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
478 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
479 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
480 .mpu.addr = TPS65917_REG_ADDR_SMPS1,
481 .mpu.pmic = &tps659038,
482 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
483
484 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
485 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
486 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
487 .core.addr = TPS65917_REG_ADDR_SMPS2,
488 .core.pmic = &tps659038,
489
490 /*
491 * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
492 * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
493 */
494 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
495 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
496 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
497 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
498 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
499 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
500 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
501 .gpu.addr = TPS65917_REG_ADDR_SMPS3,
502 .gpu.pmic = &tps659038,
503 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
504
505 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
506 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
507 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
508 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
509 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
510 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
511 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
512 .eve.addr = TPS65917_REG_ADDR_SMPS3,
513 .eve.pmic = &tps659038,
514 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
515
516 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
517 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
518 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
519 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
520 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
521 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
522 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
523 .iva.addr = TPS65917_REG_ADDR_SMPS3,
524 .iva.pmic = &tps659038,
525 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
526 };
527
528 struct vcores_data dra718_volts = {
529 /*
530 * In the case of dra71x GPU MPU and CORE
531 * are all powered up by BUCK0 of LP873X PMIC
532 */
533 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
534 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
535 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
536 .mpu.addr = LP873X_REG_ADDR_BUCK0,
537 .mpu.pmic = &lp8733,
538 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
539
540 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
541 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
542 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
543 .core.addr = LP873X_REG_ADDR_BUCK0,
544 .core.pmic = &lp8733,
545
546 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
547 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
548 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
549 .gpu.addr = LP873X_REG_ADDR_BUCK0,
550 .gpu.pmic = &lp8733,
551 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
552
553 /*
554 * The DSPEVE and IVA rails are grouped on DRA71x-evm
555 * and are powered by BUCK1 of LP873X PMIC
556 */
557 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
558 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
559 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
560 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
561 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
562 .eve.addr = LP873X_REG_ADDR_BUCK1,
563 .eve.pmic = &lp8733,
564 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
565
566 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
567 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
568 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
569 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
570 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
571 .iva.addr = LP873X_REG_ADDR_BUCK1,
572 .iva.pmic = &lp8733,
573 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
574 };
575
get_voltrail_opp(int rail_offset)576 int get_voltrail_opp(int rail_offset)
577 {
578 int opp;
579
580 switch (rail_offset) {
581 case VOLT_MPU:
582 opp = DRA7_MPU_OPP;
583 /* DRA71x supports only OPP_NOM for MPU */
584 if (board_is_dra71x_evm())
585 opp = OPP_NOM;
586 break;
587 case VOLT_CORE:
588 opp = DRA7_CORE_OPP;
589 /* DRA71x supports only OPP_NOM for CORE */
590 if (board_is_dra71x_evm())
591 opp = OPP_NOM;
592 break;
593 case VOLT_GPU:
594 opp = DRA7_GPU_OPP;
595 /* DRA71x supports only OPP_NOM for GPU */
596 if (board_is_dra71x_evm())
597 opp = OPP_NOM;
598 break;
599 case VOLT_EVE:
600 opp = DRA7_DSPEVE_OPP;
601 /*
602 * DRA71x does not support OPP_OD for EVE.
603 * If OPP_OD is selected by menuconfig, fallback
604 * to OPP_NOM.
605 */
606 if (board_is_dra71x_evm() && opp == OPP_OD)
607 opp = OPP_NOM;
608 break;
609 case VOLT_IVA:
610 opp = DRA7_IVA_OPP;
611 /*
612 * DRA71x does not support OPP_OD for IVA.
613 * If OPP_OD is selected by menuconfig, fallback
614 * to OPP_NOM.
615 */
616 if (board_is_dra71x_evm() && opp == OPP_OD)
617 opp = OPP_NOM;
618 break;
619 default:
620 opp = OPP_NOM;
621 }
622
623 return opp;
624 }
625
626 /**
627 * @brief board_init
628 *
629 * Return: 0
630 */
board_init(void)631 int board_init(void)
632 {
633 gpmc_init();
634 gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
635
636 return 0;
637 }
638
dram_init_banksize(void)639 int dram_init_banksize(void)
640 {
641 u64 ram_size;
642
643 ram_size = board_ti_get_emif_size();
644
645 gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
646 gd->bd->bi_dram[0].size = get_effective_memsize();
647 if (ram_size > CFG_MAX_MEM_MAPPED) {
648 gd->bd->bi_dram[1].start = 0x200000000;
649 gd->bd->bi_dram[1].size = ram_size - CFG_MAX_MEM_MAPPED;
650 }
651
652 return 0;
653 }
654
655 #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
device_okay(const char * path)656 static int device_okay(const char *path)
657 {
658 int node;
659
660 node = fdt_path_offset(gd->fdt_blob, path);
661 if (node < 0)
662 return 0;
663
664 return fdtdec_get_is_enabled(gd->fdt_blob, node);
665 }
666 #endif
667
board_late_init(void)668 int board_late_init(void)
669 {
670 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
671 char *name = "unknown";
672
673 if (is_dra72x()) {
674 if (board_is_dra72x_revc_or_later())
675 name = "dra72x-revc";
676 else if (board_is_dra71x_evm())
677 name = "dra71x";
678 else
679 name = "dra72x";
680 } else if (is_dra76x_abz()) {
681 name = "dra76x_abz";
682 } else if (is_dra76x_acd()) {
683 name = "dra76x_acd";
684 } else {
685 name = "dra7xx";
686 }
687
688 set_board_info_env(name);
689
690 /*
691 * Default FIT boot on HS devices. Non FIT images are not allowed
692 * on HS devices.
693 */
694 if (get_device_type() == HS_DEVICE)
695 env_set("boot_fit", "1");
696
697 omap_die_id_serial();
698 omap_set_fastboot_vars();
699
700 /*
701 * Hook the LDO1 regulator to EN pin. This applies only to LP8733
702 * Rest all regulators are hooked to EN Pin at reset.
703 */
704 if (board_is_dra71x_evm())
705 palmas_i2c_write_u8(LP873X_I2C_SLAVE_ADDR, 0x9, 0x7);
706 #endif
707 #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
708 if (device_okay("/ocp/omap_dwc3_1@48880000"))
709 enable_usb_clocks(0);
710 if (device_okay("/ocp/omap_dwc3_2@488c0000"))
711 enable_usb_clocks(1);
712 #endif
713 return 0;
714 }
715
716 #ifdef CONFIG_XPL_BUILD
do_board_detect(void)717 void do_board_detect(void)
718 {
719 int rc;
720
721 rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
722 CONFIG_EEPROM_CHIP_ADDRESS);
723 if (rc)
724 printf("ti_i2c_eeprom_init failed %d\n", rc);
725 }
726
727 #else
728
do_board_detect(void)729 void do_board_detect(void)
730 {
731 char *bname = NULL;
732 int rc;
733
734 rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
735 CONFIG_EEPROM_CHIP_ADDRESS);
736 if (rc)
737 printf("ti_i2c_eeprom_init failed %d\n", rc);
738
739 if (board_is_dra74x_evm()) {
740 bname = "DRA74x EVM";
741 } else if (board_is_dra72x_evm()) {
742 bname = "DRA72x EVM";
743 } else if (board_is_dra71x_evm()) {
744 bname = "DRA71x EVM";
745 } else if (board_is_dra76x_evm()) {
746 bname = "DRA76x EVM";
747 } else {
748 /* If EEPROM is not populated */
749 if (is_dra72x())
750 bname = "DRA72x EVM";
751 else
752 bname = "DRA74x EVM";
753 }
754
755 if (bname)
756 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
757 "Board: %s REV %s\n", bname, board_ti_get_rev());
758 }
759 #endif /* CONFIG_XPL_BUILD */
760
vcores_init(void)761 void vcores_init(void)
762 {
763 if (board_is_dra74x_evm()) {
764 *omap_vcores = &dra752_volts;
765 } else if (board_is_dra72x_evm()) {
766 *omap_vcores = &dra722_volts;
767 } else if (board_is_dra71x_evm()) {
768 *omap_vcores = &dra718_volts;
769 } else if (board_is_dra76x_evm()) {
770 *omap_vcores = &dra76x_volts;
771 } else {
772 /* If EEPROM is not populated */
773 if (is_dra72x())
774 *omap_vcores = &dra722_volts;
775 else
776 *omap_vcores = &dra752_volts;
777 }
778 }
779
set_muxconf_regs(void)780 void set_muxconf_regs(void)
781 {
782 do_set_mux32((*ctrl)->control_padconf_core_base,
783 early_padconf, ARRAY_SIZE(early_padconf));
784 }
785
786 #if defined(CONFIG_MTD_RAW_NAND)
nand_sw_detect(void)787 static int nand_sw_detect(void)
788 {
789 int rc;
790 uchar data[2];
791 struct udevice *dev;
792
793 rc = i2c_get_chip_for_busnum(NAND_PCF8575_I2C_BUS_NUM,
794 NAND_PCF8575_ADDR, 0, &dev);
795 if (rc)
796 return -1;
797
798 rc = dm_i2c_read(dev, 0, (uint8_t *)&data, sizeof(data));
799 if (rc)
800 return -1;
801
802 /* We are only interested in P10 and P11 on PCF8575 which is equal to
803 * bits 8 and 9.
804 */
805 data[1] = data[1] & 0x3;
806
807 /* Ensure only P11 is set and P10 is cleared. This ensures only
808 * NAND (P10) is configured and not NOR (P11) which are both low
809 * true signals. NAND and NOR settings should not be enabled at
810 * the same time.
811 */
812 if (data[1] == 0x2)
813 return 0;
814
815 return -1;
816 }
817 #else
nand_sw_detect(void)818 int nand_sw_detect(void)
819 {
820 return -1;
821 }
822 #endif
823
824 #ifdef CONFIG_IODELAY_RECALIBRATION
recalibrate_iodelay(void)825 void recalibrate_iodelay(void)
826 {
827 struct pad_conf_entry const *pads, *delta_pads = NULL;
828 struct iodelay_cfg_entry const *iodelay;
829 int npads, niodelays, delta_npads = 0;
830 int ret;
831
832 switch (omap_revision()) {
833 case DRA722_ES1_0:
834 case DRA722_ES2_0:
835 case DRA722_ES2_1:
836 pads = dra72x_core_padconf_array_common;
837 npads = ARRAY_SIZE(dra72x_core_padconf_array_common);
838 if (board_is_dra71x_evm()) {
839 pads = dra71x_core_padconf_array;
840 npads = ARRAY_SIZE(dra71x_core_padconf_array);
841 iodelay = dra71_iodelay_cfg_array;
842 niodelays = ARRAY_SIZE(dra71_iodelay_cfg_array);
843 /* If SW8 on the EVM is set to enable NAND then
844 * overwrite the pins used by VOUT3 with NAND.
845 */
846 if (!nand_sw_detect()) {
847 delta_pads = dra71x_nand_padconf_array;
848 delta_npads =
849 ARRAY_SIZE(dra71x_nand_padconf_array);
850 } else {
851 delta_pads = dra71x_vout3_padconf_array;
852 delta_npads =
853 ARRAY_SIZE(dra71x_vout3_padconf_array);
854 }
855
856 } else if (board_is_dra72x_revc_or_later()) {
857 delta_pads = dra72x_rgmii_padconf_array_revc;
858 delta_npads =
859 ARRAY_SIZE(dra72x_rgmii_padconf_array_revc);
860 iodelay = dra72_iodelay_cfg_array_revc;
861 niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revc);
862 } else {
863 delta_pads = dra72x_rgmii_padconf_array_revb;
864 delta_npads =
865 ARRAY_SIZE(dra72x_rgmii_padconf_array_revb);
866 iodelay = dra72_iodelay_cfg_array_revb;
867 niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revb);
868 }
869 break;
870 case DRA752_ES1_0:
871 case DRA752_ES1_1:
872 pads = dra74x_core_padconf_array;
873 npads = ARRAY_SIZE(dra74x_core_padconf_array);
874 iodelay = dra742_es1_1_iodelay_cfg_array;
875 niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
876 break;
877 case DRA762_ACD_ES1_0:
878 case DRA762_ES1_0:
879 pads = dra76x_core_padconf_array;
880 npads = ARRAY_SIZE(dra76x_core_padconf_array);
881 iodelay = dra76x_es1_0_iodelay_cfg_array;
882 niodelays = ARRAY_SIZE(dra76x_es1_0_iodelay_cfg_array);
883 break;
884 default:
885 case DRA752_ES2_0:
886 case DRA762_ABZ_ES1_0:
887 pads = dra74x_core_padconf_array;
888 npads = ARRAY_SIZE(dra74x_core_padconf_array);
889 iodelay = dra742_es2_0_iodelay_cfg_array;
890 niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array);
891 /* Setup port1 and port2 for rgmii with 'no-id' mode */
892 clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK |
893 RGMII1_ID_MODE_N_MASK);
894 break;
895 }
896 /* Setup I/O isolation */
897 ret = __recalibrate_iodelay_start();
898 if (ret)
899 goto err;
900
901 /* Do the muxing here */
902 do_set_mux32((*ctrl)->control_padconf_core_base, pads, npads);
903
904 /* Now do the weird minor deltas that should be safe */
905 if (delta_npads)
906 do_set_mux32((*ctrl)->control_padconf_core_base,
907 delta_pads, delta_npads);
908
909 if (is_dra76x())
910 /* Set mux for MCAN instead of DCAN1 */
911 clrsetbits_le32((*ctrl)->control_core_control_spare_rw,
912 MCAN_SEL_ALT_MASK, MCAN_SEL);
913
914 /* Setup IOdelay configuration */
915 ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
916 err:
917 /* Closeup.. remove isolation */
918 __recalibrate_iodelay_end(ret);
919 }
920 #endif
921
922 #if defined(CONFIG_MMC)
board_mmc_init(struct bd_info * bis)923 int board_mmc_init(struct bd_info *bis)
924 {
925 omap_mmc_init(0, 0, 0, -1, -1);
926 omap_mmc_init(1, 0, 0, -1, -1);
927 return 0;
928 }
929
board_mmc_poweron_ldo(uint voltage)930 void board_mmc_poweron_ldo(uint voltage)
931 {
932 if (board_is_dra71x_evm()) {
933 if (voltage == LDO_VOLT_3V0)
934 voltage = 0x19;
935 else if (voltage == LDO_VOLT_1V8)
936 voltage = 0xa;
937 lp873x_mmc1_poweron_ldo(voltage);
938 } else if (board_is_dra76x_evm()) {
939 palmas_mmc1_poweron_ldo(LDO4_VOLTAGE, LDO4_CTRL, voltage);
940 } else {
941 palmas_mmc1_poweron_ldo(LDO1_VOLTAGE, LDO1_CTRL, voltage);
942 }
943 }
944
945 static const struct mmc_platform_fixups dra7x_es1_1_mmc1_fixups = {
946 .hw_rev = "rev11",
947 .unsupported_caps = MMC_CAP(MMC_HS_200) |
948 MMC_CAP(UHS_SDR104),
949 .max_freq = 96000000,
950 };
951
952 static const struct mmc_platform_fixups dra7x_es1_1_mmc23_fixups = {
953 .hw_rev = "rev11",
954 .unsupported_caps = MMC_CAP(MMC_HS_200) |
955 MMC_CAP(UHS_SDR104) |
956 MMC_CAP(UHS_SDR50),
957 .max_freq = 48000000,
958 };
959
platform_fixups_mmc(uint32_t addr)960 const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
961 {
962 switch (omap_revision()) {
963 case DRA752_ES1_0:
964 case DRA752_ES1_1:
965 if (addr == OMAP_HSMMC1_BASE)
966 return &dra7x_es1_1_mmc1_fixups;
967 else
968 return &dra7x_es1_1_mmc23_fixups;
969 default:
970 return NULL;
971 }
972 }
973 #endif
974
975 #if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
spl_start_uboot(void)976 int spl_start_uboot(void)
977 {
978 /* break into full u-boot on 'c' */
979 if (serial_tstc() && serial_getc() == 'c')
980 return 1;
981
982 #ifdef CONFIG_SPL_ENV_SUPPORT
983 env_init();
984 env_load();
985 if (env_get_yesno("boot_os") != 1)
986 return 1;
987 #endif
988
989 return 0;
990 }
991 #endif
992
993 #ifdef CONFIG_BOARD_EARLY_INIT_F
994 /* VTT regulator enable */
vtt_regulator_enable(void)995 static inline void vtt_regulator_enable(void)
996 {
997 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
998 return;
999
1000 /* Do not enable VTT for DRA722 or DRA76x */
1001 if (is_dra72x() || is_dra76x())
1002 return;
1003
1004 /*
1005 * EVM Rev G and later use gpio7_11 for DDR3 termination.
1006 * This is safe enough to do on older revs.
1007 */
1008 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
1009 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
1010 }
1011
board_early_init_f(void)1012 int board_early_init_f(void)
1013 {
1014 vtt_regulator_enable();
1015 return 0;
1016 }
1017 #endif
1018
1019 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
ft_board_setup(void * blob,struct bd_info * bd)1020 int ft_board_setup(void *blob, struct bd_info *bd)
1021 {
1022 ft_cpu_setup(blob, bd);
1023
1024 return 0;
1025 }
1026 #endif
1027
1028 #ifdef CONFIG_SPL_LOAD_FIT
board_fit_config_name_match(const char * name)1029 int board_fit_config_name_match(const char *name)
1030 {
1031 if (is_dra72x()) {
1032 if (board_is_dra71x_evm()) {
1033 if (!strcmp(name, "dra71-evm"))
1034 return 0;
1035 }else if(board_is_dra72x_revc_or_later()) {
1036 if (!strcmp(name, "dra72-evm-revc"))
1037 return 0;
1038 } else if (!strcmp(name, "dra72-evm")) {
1039 return 0;
1040 }
1041 } else if (is_dra76x_acd() && !strcmp(name, "dra76-evm")) {
1042 return 0;
1043 } else if (!is_dra72x() && !is_dra76x_acd() &&
1044 !strcmp(name, "dra7-evm")) {
1045 return 0;
1046 }
1047
1048 return -1;
1049 }
1050 #endif
1051
1052 #if IS_ENABLED(CONFIG_FASTBOOT) && !CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
fastboot_set_reboot_flag(enum fastboot_reboot_reason reason)1053 int fastboot_set_reboot_flag(enum fastboot_reboot_reason reason)
1054 {
1055 if (reason != FASTBOOT_REBOOT_REASON_BOOTLOADER)
1056 return -ENOTSUPP;
1057
1058 printf("Setting reboot to fastboot flag ...\n");
1059 env_set("dofastboot", "1");
1060 env_save();
1061 return 0;
1062 }
1063 #endif
1064