1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
4 * Copyright (C) Jasbir Matharu
5 * Copyright (C) UDOO Team
6 *
7 * Author: Breno Lima <breno.lima@nxp.com>
8 * Author: Francesco Montefoschi <francesco.monte@gmail.com>
9 */
10
11 #include <init.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/crm_regs.h>
14 #include <asm/arch/imx-regs.h>
15 #include <asm/arch/iomux.h>
16 #include <asm/arch/mx6-pins.h>
17 #include <asm/global_data.h>
18 #include <asm/gpio.h>
19 #include <asm/mach-imx/iomux-v3.h>
20 #include <asm/sections.h>
21 #include <dm.h>
22 #include <env.h>
23 #include <mmc.h>
24 #include <fsl_esdhc_imx.h>
25 #include <asm/arch/crm_regs.h>
26 #include <asm/io.h>
27 #include <asm/mach-imx/mxc_i2c.h>
28 #include <asm/arch/sys_proto.h>
29 #include <spl.h>
30 #include <linux/delay.h>
31 #include <linux/sizes.h>
32 #include <i2c.h>
33 #include <power/pmic.h>
34 #include <power/pfuze3000_pmic.h>
35 #include <malloc.h>
36
37 DECLARE_GLOBAL_DATA_PTR;
38
39 enum {
40 UDOO_NEO_TYPE_BASIC,
41 UDOO_NEO_TYPE_BASIC_KS,
42 UDOO_NEO_TYPE_FULL,
43 UDOO_NEO_TYPE_EXTENDED,
44 };
45
46 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
47 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
48 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
49
50 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
51 PAD_CTL_SPEED_MED | \
52 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
53
54 #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
55 PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
56
57 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
58 PAD_CTL_SPEED_MED | PAD_CTL_SRE_FAST)
59
60 #define BOARD_DETECT_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
61 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
62 PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
63 #define BOARD_DETECT_PAD_CFG (MUX_PAD_CTRL(BOARD_DETECT_PAD_CTRL) | \
64 MUX_MODE_SION)
65
66 #define OCRAM_START 0x8f8000
67
dram_init(void)68 int dram_init(void)
69 {
70 gd->ram_size = imx_ddr_size();
71 return 0;
72 }
73
power_init_board(void)74 int power_init_board(void)
75 {
76 struct udevice *dev;
77 int ret, dev_id, rev_id;
78
79 ret = pmic_get("pfuze3000@8", &dev);
80 if (ret == -ENODEV)
81 return 0;
82 if (ret != 0)
83 return ret;
84
85 dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
86 rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
87 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
88
89 pmic_clrsetbits(dev, PFUZE3000_LDOGCTL, 0, 1);
90
91 return 0;
92 }
93
94 static iomux_v3_cfg_t const usdhc2_pads[] = {
95 MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
96 MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
97 MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
98 MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
99 MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
100 MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
101 /* CD pin */
102 MX6_PAD_SD1_DATA0__GPIO6_IO_2 | MUX_PAD_CTRL(NO_PAD_CTRL),
103 /* Power */
104 MX6_PAD_SD1_CMD__GPIO6_IO_1 | MUX_PAD_CTRL(NO_PAD_CTRL),
105 };
106
107 static iomux_v3_cfg_t const phy_control_pads[] = {
108 /* 25MHz Ethernet PHY Clock */
109 MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M |
110 MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
111 };
112
113 static iomux_v3_cfg_t const peri_3v3_pads[] = {
114 MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
115 };
116
setup_fec(void)117 static int setup_fec(void)
118 {
119 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
120 int reg;
121
122 imx_iomux_v3_setup_multiple_pads(phy_control_pads,
123 ARRAY_SIZE(phy_control_pads));
124
125 /* Reset PHY */
126 gpio_request(IMX_GPIO_NR(2, 1), "enet_rst");
127 gpio_direction_output(IMX_GPIO_NR(2, 1) , 0);
128 udelay(10000);
129 gpio_set_value(IMX_GPIO_NR(2, 1), 1);
130 udelay(100);
131
132 reg = readl(&anatop->pll_enet);
133 reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
134 writel(reg, &anatop->pll_enet);
135
136 return enable_fec_anatop_clock(0, ENET_25MHZ);
137 }
138
board_string(int type)139 static char *board_string(int type)
140 {
141 switch (type) {
142 case UDOO_NEO_TYPE_BASIC:
143 return "BASIC";
144 case UDOO_NEO_TYPE_BASIC_KS:
145 return "BASICKS";
146 case UDOO_NEO_TYPE_FULL:
147 return "FULL";
148 case UDOO_NEO_TYPE_EXTENDED:
149 return "EXTENDED";
150 }
151 return "UNDEFINED";
152 }
153
board_init(void)154 int board_init(void)
155 {
156 int *board_type = (int *)OCRAM_START;
157
158 /* Address of boot parameters */
159 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
160
161 /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
162 imx_iomux_v3_setup_multiple_pads(peri_3v3_pads,
163 ARRAY_SIZE(peri_3v3_pads));
164
165 /* Active high for ncp692 */
166 gpio_request(IMX_GPIO_NR(4, 16), "ncp692");
167 gpio_direction_output(IMX_GPIO_NR(4, 16) , 1);
168
169 printf("Board: UDOO Neo %s\n", board_string(*board_type));
170
171 setup_fec();
172
173 return 0;
174 }
175
176 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
177 {USDHC2_BASE_ADDR},
178 };
179
180 #define USDHC2_PWR_GPIO IMX_GPIO_NR(6, 1)
181 #define USDHC2_CD_GPIO IMX_GPIO_NR(6, 2)
182
board_mmc_getcd(struct mmc * mmc)183 int board_mmc_getcd(struct mmc *mmc)
184 {
185 return !gpio_get_value(USDHC2_CD_GPIO);
186 }
187
board_mmc_init(struct bd_info * bis)188 int board_mmc_init(struct bd_info *bis)
189 {
190 SETUP_IOMUX_PADS(usdhc2_pads);
191 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
192 usdhc_cfg[0].max_bus_width = 4;
193 gpio_request(IMX_GPIO_NR(6, 1), "usdhc2_pwr");
194 gpio_request(IMX_GPIO_NR(6, 2), "usdhc2_cd");
195 gpio_direction_input(USDHC2_CD_GPIO);
196 gpio_direction_output(USDHC2_PWR_GPIO, 1);
197
198 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
199 }
200
board_late_init(void)201 int board_late_init(void)
202 {
203 int *board_type = (int *)OCRAM_START;
204
205 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
206 env_set("board_name", board_string(*board_type));
207 #endif
208
209 return 0;
210 }
211
212 #ifdef CONFIG_XPL_BUILD
213
214 #include <linux/libfdt.h>
215 #include <asm/arch/mx6-ddr.h>
216
217 static const iomux_v3_cfg_t board_recognition_pads[] = {
218 /*Connected to R184*/
219 MX6_PAD_NAND_READY_B__GPIO4_IO_13 | BOARD_DETECT_PAD_CFG,
220 /*Connected to R185*/
221 MX6_PAD_NAND_ALE__GPIO4_IO_0 | BOARD_DETECT_PAD_CFG,
222 };
223
get_board_value(void)224 static int get_board_value(void)
225 {
226 int r184, r185;
227
228 imx_iomux_v3_setup_multiple_pads(board_recognition_pads,
229 ARRAY_SIZE(board_recognition_pads));
230
231 gpio_request(IMX_GPIO_NR(4, 13), "r184");
232 gpio_request(IMX_GPIO_NR(4, 0), "r185");
233 gpio_direction_input(IMX_GPIO_NR(4, 13));
234 gpio_direction_input(IMX_GPIO_NR(4, 0));
235
236 r184 = gpio_get_value(IMX_GPIO_NR(4, 13));
237 r185 = gpio_get_value(IMX_GPIO_NR(4, 0));
238
239 /*
240 * Machine selection -
241 * Machine r184, r185
242 * ---------------------------------
243 * Basic 0 0
244 * Basic Ks 0 1
245 * Full 1 0
246 * Extended 1 1
247 */
248
249 return (r184 << 1) + r185;
250 }
251
252 static const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
253 .dram_dqm0 = 0x00000028,
254 .dram_dqm1 = 0x00000028,
255 .dram_dqm2 = 0x00000028,
256 .dram_dqm3 = 0x00000028,
257 .dram_ras = 0x00000020,
258 .dram_cas = 0x00000020,
259 .dram_odt0 = 0x00000020,
260 .dram_odt1 = 0x00000020,
261 .dram_sdba2 = 0x00000000,
262 .dram_sdcke0 = 0x00003000,
263 .dram_sdcke1 = 0x00003000,
264 .dram_sdclk_0 = 0x00000030,
265 .dram_sdqs0 = 0x00000028,
266 .dram_sdqs1 = 0x00000028,
267 .dram_sdqs2 = 0x00000028,
268 .dram_sdqs3 = 0x00000028,
269 .dram_reset = 0x00000020,
270 };
271
272 static const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = {
273 .grp_addds = 0x00000020,
274 .grp_ddrmode_ctl = 0x00020000,
275 .grp_ddrpke = 0x00000000,
276 .grp_ddrmode = 0x00020000,
277 .grp_b0ds = 0x00000028,
278 .grp_b1ds = 0x00000028,
279 .grp_ctlds = 0x00000020,
280 .grp_ddr_type = 0x000c0000,
281 .grp_b2ds = 0x00000028,
282 .grp_b3ds = 0x00000028,
283 };
284
285 static const struct mx6_mmdc_calibration neo_mmcd_calib = {
286 .p0_mpwldectrl0 = 0x000E000B,
287 .p0_mpwldectrl1 = 0x000E0010,
288 .p0_mpdgctrl0 = 0x41600158,
289 .p0_mpdgctrl1 = 0x01500140,
290 .p0_mprddlctl = 0x3A383E3E,
291 .p0_mpwrdlctl = 0x3A383C38,
292 };
293
294 static const struct mx6_mmdc_calibration neo_basic_mmcd_calib = {
295 .p0_mpwldectrl0 = 0x001E0022,
296 .p0_mpwldectrl1 = 0x001C0019,
297 .p0_mpdgctrl0 = 0x41540150,
298 .p0_mpdgctrl1 = 0x01440138,
299 .p0_mprddlctl = 0x403E4644,
300 .p0_mpwrdlctl = 0x3C3A4038,
301 };
302
303 /* MT41K256M16 */
304 static struct mx6_ddr3_cfg neo_mem_ddr = {
305 .mem_speed = 1600,
306 .density = 4,
307 .width = 16,
308 .banks = 8,
309 .rowaddr = 15,
310 .coladdr = 10,
311 .pagesz = 2,
312 .trcd = 1375,
313 .trcmin = 4875,
314 .trasmin = 3500,
315 };
316
317 /* MT41K128M16 */
318 static struct mx6_ddr3_cfg neo_basic_mem_ddr = {
319 .mem_speed = 1600,
320 .density = 2,
321 .width = 16,
322 .banks = 8,
323 .rowaddr = 14,
324 .coladdr = 10,
325 .pagesz = 2,
326 .trcd = 1375,
327 .trcmin = 4875,
328 .trasmin = 3500,
329 };
330
ccgr_init(void)331 static void ccgr_init(void)
332 {
333 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
334
335 writel(0xFFFFFFFF, &ccm->CCGR0);
336 writel(0xFFFFFFFF, &ccm->CCGR1);
337 writel(0xFFFFFFFF, &ccm->CCGR2);
338 writel(0xFFFFFFFF, &ccm->CCGR3);
339 writel(0xFFFFFFFF, &ccm->CCGR4);
340 writel(0xFFFFFFFF, &ccm->CCGR5);
341 writel(0xFFFFFFFF, &ccm->CCGR6);
342 writel(0xFFFFFFFF, &ccm->CCGR7);
343 }
344
spl_dram_init(void)345 static void spl_dram_init(void)
346 {
347 int *board_type = (int *)OCRAM_START;
348
349 struct mx6_ddr_sysinfo sysinfo = {
350 .dsize = 1, /* width of data bus: 1 = 32 bits */
351 .cs_density = 24,
352 .ncs = 1,
353 .cs1_mirror = 0,
354 .rtt_wr = 2,
355 .rtt_nom = 2, /* RTT_Nom = RZQ/2 */
356 .walat = 1, /* Write additional latency */
357 .ralat = 5, /* Read additional latency */
358 .mif3_mode = 3, /* Command prediction working mode */
359 .bi_on = 1, /* Bank interleaving enabled */
360 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
361 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
362 };
363
364 *board_type = get_board_value();
365
366 mx6sx_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs);
367 if (*board_type == UDOO_NEO_TYPE_BASIC ||
368 *board_type == UDOO_NEO_TYPE_BASIC_KS)
369 mx6_dram_cfg(&sysinfo, &neo_basic_mmcd_calib,
370 &neo_basic_mem_ddr);
371 else
372 mx6_dram_cfg(&sysinfo, &neo_mmcd_calib, &neo_mem_ddr);
373 }
374
board_init_f(ulong dummy)375 void board_init_f(ulong dummy)
376 {
377 ccgr_init();
378
379 /* setup AIPS and disable watchdog */
380 arch_cpu_init();
381
382 /* setup GP timer */
383 timer_init();
384
385 /* Enable device tree and early DM support*/
386 spl_early_init();
387
388 /* UART clocks enabled and gd valid - init serial console */
389 preloader_console_init();
390
391 /* DDR initialization */
392 spl_dram_init();
393
394 /* Clear the BSS. */
395 memset(__bss_start, 0, __bss_end - __bss_start);
396
397 /* load/boot image from boot device */
398 board_init_r(NULL, 0);
399 }
400
401 #endif
402