1if TARGET_MICROBLAZE_GENERIC
2
3config SYS_BOARD
4	default "microblaze-generic"
5
6config SYS_VENDOR
7	default "xilinx"
8
9config XILINX_MICROBLAZE0_USE_MSR_INSTR
10	int "USE_MSR_INSTR range (0:1)"
11	default 0
12
13config XILINX_MICROBLAZE0_USE_PCMP_INSTR
14	int "USE_PCMP_INSTR range (0:1)"
15	default 0
16
17config XILINX_MICROBLAZE0_USE_BARREL
18	int "USE_BARREL range (0:1)"
19	default 0
20
21config XILINX_MICROBLAZE0_USE_DIV
22	int "USE_DIV range (0:1)"
23	default 0
24
25config XILINX_MICROBLAZE0_USE_HW_MUL
26	int "USE_HW_MUL values (0=NONE, 1=MUL32, 2=MUL64)"
27	default 0
28
29config XILINX_MICROBLAZE0_HW_VER
30	string "Core version number"
31	default "7.10.d"
32
33config XILINX_MICROBLAZE0_FPGA_FAMILY
34	string "Targeted FPGA family"
35	default "virtex5"
36	help
37	  This option contains info about the target FPGA architecture
38	  (Zynq-7000, UltraScale+ Kintex, etc) that the MicroBlaze soft core is
39	  implemented on. It corresponds to the C_FAMILY hdl parameter.
40
41config XILINX_MICROBLAZE0_USR_EXCEP
42	bool "MicroBlaze user exception support"
43	default y
44	help
45	  Enable this option in order to install the user exception handler
46	  (_exception_handler routine from arch/microblaze/cpu/exception.c) in
47	  the exception vector table. The user exception vector is located at
48	  C_BASE_VECTORS + 0x8 address.
49
50config XILINX_MICROBLAZE0_DELAY_SLOT_EXCEP
51	bool "MicroBlaze delay slot exception support"
52	default y
53	help
54	  Enable this option if the MicroBlaze processor supports exceptions
55	  caused by delay slot instructions (processor version >= v5.00). When
56	  enabled, the hw exception handler will print a message indicating
57	  whether the exception was triggered by a delay slot instruction.
58
59config XILINX_MICROBLAZE0_VECTOR_BASE_ADDR
60	hex "Location of MicroBlaze vectors"
61	default 0x0
62	help
63	  Memory address location of the exception vector table. It is
64	  configurable via the C_BASE_VECTORS hdl parameter.
65
66config XILINX_MICROBLAZE0_USE_WDC
67	bool "MicroBlaze wdc instruction support"
68	default y
69	help
70	  Enable this option if the MicroBlaze processor is configured with
71	  support for the "wdc" (Write to Data Cache) instruction.
72
73config SPL_XILINX_MICROBLAZE0_USE_WDC
74	bool
75	default XILINX_MICROBLAZE0_USE_WDC
76
77config XILINX_MICROBLAZE0_USE_WIC
78	bool "MicroBlaze wic instruction support"
79	default y
80	help
81	  Enable this option if the MicroBlaze processor is configured with
82	  support for the "wic" (Write to Instruction Cache) instruction.
83
84config SPL_XILINX_MICROBLAZE0_USE_WIC
85	bool
86	default XILINX_MICROBLAZE0_USE_WIC
87
88config XILINX_MICROBLAZE0_DCACHE_SIZE
89	int "Default data cache size"
90	default 32768
91	help
92	  This fallback size will be used when no dcache info can be found in
93	  the device tree, or when the data cache is flushed very early in the
94	  boot process, before device tree is available.
95
96config XILINX_MICROBLAZE0_ICACHE_SIZE
97	int "Default instruction cache size"
98	default 32768
99	help
100	  This fallback size will be used when no icache info can be found in
101	  the device tree, or when the instruction cache is flushed very early
102	  in the boot process, before device tree is available.
103
104config XILINX_MICROBLAZE0_PVR
105	bool "MicroBlaze PVR support"
106	help
107	  Enables helper functions and macros needed to manipulate PVR
108	  (Processor Version Register) data. Currently, only the microblaze
109	  UCLASS_CPU driver makes use of this feature to retrieve CPU info at
110	  runtime.
111
112endif
113