1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
4 * (C) Copyright 2013 - 2018 Xilinx, Inc.
5 */
6
7 #include <config.h>
8 #include <debug_uart.h>
9 #include <dfu.h>
10 #include <efi_loader.h>
11 #include <init.h>
12 #include <log.h>
13 #include <dm/uclass.h>
14 #include <env.h>
15 #include <env_internal.h>
16 #include <fdtdec.h>
17 #include <fpga.h>
18 #include <malloc.h>
19 #include <memalign.h>
20 #include <mmc.h>
21 #include <watchdog.h>
22 #include <wdt.h>
23 #include <zynqpl.h>
24 #include <asm/global_data.h>
25 #include <asm/arch/hardware.h>
26 #include <asm/arch/sys_proto.h>
27 #include "../common/board.h"
28
29 DECLARE_GLOBAL_DATA_PTR;
30
31 #if !defined(CONFIG_XPL_BUILD) && defined(CONFIG_DEBUG_UART_BOARD_INIT)
board_debug_uart_init(void)32 void board_debug_uart_init(void)
33 {
34 /* Add initialization sequence if UART is not configured */
35 }
36 #endif
37
board_init(void)38 int board_init(void)
39 {
40 if (IS_ENABLED(CONFIG_XPL_BUILD))
41 printf("Silicon version:\t%d\n", zynq_get_silicon_version());
42
43 if (CONFIG_IS_ENABLED(DM_I2C) && CONFIG_IS_ENABLED(I2C_EEPROM))
44 xilinx_read_eeprom();
45
46 return 0;
47 }
48
board_late_init(void)49 int board_late_init(void)
50 {
51 int env_targets_len = 0;
52 const char *mode;
53 char *new_targets;
54 char *env_targets;
55
56 if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT))
57 configure_capsule_updates();
58
59 if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
60 debug("Saved variables - Skipping\n");
61 return 0;
62 }
63
64 if (!IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG))
65 return 0;
66
67 switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
68 case ZYNQ_BM_QSPI:
69 mode = "qspi";
70 env_set("modeboot", "qspiboot");
71 break;
72 case ZYNQ_BM_NAND:
73 mode = "nand";
74 env_set("modeboot", "nandboot");
75 break;
76 case ZYNQ_BM_NOR:
77 mode = "nor";
78 env_set("modeboot", "norboot");
79 break;
80 case ZYNQ_BM_SD:
81 mode = "mmc0";
82 env_set("modeboot", "sdboot");
83 break;
84 case ZYNQ_BM_JTAG:
85 mode = "jtag pxe dhcp";
86 env_set("modeboot", "jtagboot");
87 break;
88 default:
89 mode = "";
90 env_set("modeboot", "");
91 break;
92 }
93
94 /*
95 * One terminating char + one byte for space between mode
96 * and default boot_targets
97 */
98 env_targets = env_get("boot_targets");
99 if (env_targets)
100 env_targets_len = strlen(env_targets);
101
102 new_targets = calloc(1, strlen(mode) + env_targets_len + 2);
103 if (!new_targets)
104 return -ENOMEM;
105
106 sprintf(new_targets, "%s %s", mode,
107 env_targets ? env_targets : "");
108
109 env_set("boot_targets", new_targets);
110
111 return board_late_init_xilinx();
112 }
113
114 #if !defined(CFG_SYS_SDRAM_BASE) && !defined(CFG_SYS_SDRAM_SIZE)
dram_init_banksize(void)115 int dram_init_banksize(void)
116 {
117 return fdtdec_setup_memory_banksize();
118 }
119
dram_init(void)120 int dram_init(void)
121 {
122 if (fdtdec_setup_mem_size_base() != 0)
123 return -EINVAL;
124
125 zynq_ddrc_init();
126
127 return 0;
128 }
129 #else
dram_init(void)130 int dram_init(void)
131 {
132 gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
133 CFG_SYS_SDRAM_SIZE);
134
135 zynq_ddrc_init();
136
137 return 0;
138 }
139 #endif
140
env_get_location(enum env_operation op,int prio)141 enum env_location env_get_location(enum env_operation op, int prio)
142 {
143 u32 bootmode = zynq_slcr_get_boot_mode() & ZYNQ_BM_MASK;
144
145 if (prio)
146 return ENVL_UNKNOWN;
147
148 switch (bootmode) {
149 case ZYNQ_BM_SD:
150 if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
151 return ENVL_FAT;
152 if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4))
153 return ENVL_EXT4;
154 return ENVL_NOWHERE;
155 case ZYNQ_BM_NAND:
156 if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
157 return ENVL_NAND;
158 if (IS_ENABLED(CONFIG_ENV_IS_IN_UBI))
159 return ENVL_UBI;
160 return ENVL_NOWHERE;
161 case ZYNQ_BM_NOR:
162 case ZYNQ_BM_QSPI:
163 if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
164 return ENVL_SPI_FLASH;
165 return ENVL_NOWHERE;
166 case ZYNQ_BM_JTAG:
167 default:
168 return ENVL_NOWHERE;
169 }
170 }
171
172 #define DFU_ALT_BUF_LEN SZ_1K
173
configure_capsule_updates(void)174 void configure_capsule_updates(void)
175 {
176 ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN);
177
178 memset(buf, 0, DFU_ALT_BUF_LEN);
179
180 switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
181 #if defined(CONFIG_SPL_FS_LOAD_PAYLOAD_NAME)
182 case ZYNQ_BM_SD:
183 snprintf(buf, DFU_ALT_BUF_LEN,
184 "mmc 0=boot.bin fat 0 1;"
185 "%s fat 0 1", CONFIG_SPL_FS_LOAD_PAYLOAD_NAME);
186 break;
187 #if defined(CONFIG_SPL_SPI_LOAD)
188 case ZYNQ_BM_QSPI:
189 snprintf(buf, DFU_ALT_BUF_LEN,
190 "sf 0:0=boot.bin raw 0 0x1500000;"
191 "%s raw 0x%x 0x500000",
192 CONFIG_SPL_FS_LOAD_PAYLOAD_NAME,
193 CONFIG_SYS_SPI_U_BOOT_OFFS);
194 break;
195 #endif
196 #endif
197 default:
198 return;
199 }
200
201 update_info.dfu_string = strdup(buf);
202 debug("Capsule DFU: %s\n", update_info.dfu_string);
203 }
204