1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Andreas Heppel <aheppel@sysgo.de>
5 *
6 * (C) Copyright 2002
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
9 */
10
11 /*
12 * PCI routines
13 */
14
15 #include <bootretry.h>
16 #include <cli.h>
17 #include <command.h>
18 #include <console.h>
19 #include <dm.h>
20 #include <init.h>
21 #include <asm/processor.h>
22 #include <asm/io.h>
23 #include <pci.h>
24
25 struct pci_reg_info {
26 const char *name;
27 enum pci_size_t size;
28 u8 offset;
29 };
30
pci_byte_size(enum pci_size_t size)31 static int pci_byte_size(enum pci_size_t size)
32 {
33 switch (size) {
34 case PCI_SIZE_8:
35 return 1;
36 case PCI_SIZE_16:
37 return 2;
38 case PCI_SIZE_32:
39 default:
40 return 4;
41 }
42 }
43
pci_field_width(enum pci_size_t size)44 static int pci_field_width(enum pci_size_t size)
45 {
46 return pci_byte_size(size) * 2;
47 }
48
pci_show_regs(struct udevice * dev,struct pci_reg_info * regs)49 static void pci_show_regs(struct udevice *dev, struct pci_reg_info *regs)
50 {
51 for (; regs->name; regs++) {
52 unsigned long val;
53
54 dm_pci_read_config(dev, regs->offset, &val, regs->size);
55 printf(" %s =%*s%#.*lx\n", regs->name,
56 (int)(28 - strlen(regs->name)), "",
57 pci_field_width(regs->size), val);
58 }
59 }
60
pci_bar_show(struct udevice * dev)61 static int pci_bar_show(struct udevice *dev)
62 {
63 u8 header_type;
64 int bar_cnt, bar_id, mem_type;
65 bool is_64, is_io;
66 u32 base_low, base_high;
67 u32 size_low, size_high;
68 u64 base, size;
69 u32 reg_addr;
70 int prefetchable;
71
72 dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
73 header_type &= 0x7f;
74
75 if (header_type == PCI_HEADER_TYPE_CARDBUS) {
76 printf("CardBus doesn't support BARs\n");
77 return -ENOSYS;
78 } else if (header_type != PCI_HEADER_TYPE_NORMAL &&
79 header_type != PCI_HEADER_TYPE_BRIDGE) {
80 printf("unknown header type\n");
81 return -ENOSYS;
82 }
83
84 bar_cnt = (header_type == PCI_HEADER_TYPE_NORMAL) ? 6 : 2;
85
86 printf("ID Base Size Width Type\n");
87 printf("----------------------------------------------------------\n");
88
89 bar_id = 0;
90 reg_addr = PCI_BASE_ADDRESS_0;
91 while (bar_cnt) {
92 dm_pci_read_config32(dev, reg_addr, &base_low);
93 dm_pci_write_config32(dev, reg_addr, 0xffffffff);
94 dm_pci_read_config32(dev, reg_addr, &size_low);
95 dm_pci_write_config32(dev, reg_addr, base_low);
96 reg_addr += 4;
97
98 base = base_low & ~0xf;
99 size = size_low & ~0xf;
100 base_high = 0x0;
101 size_high = 0xffffffff;
102 is_64 = 0;
103 prefetchable = base_low & PCI_BASE_ADDRESS_MEM_PREFETCH;
104 is_io = base_low & PCI_BASE_ADDRESS_SPACE_IO;
105 mem_type = base_low & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
106
107 if (mem_type == PCI_BASE_ADDRESS_MEM_TYPE_64) {
108 dm_pci_read_config32(dev, reg_addr, &base_high);
109 dm_pci_write_config32(dev, reg_addr, 0xffffffff);
110 dm_pci_read_config32(dev, reg_addr, &size_high);
111 dm_pci_write_config32(dev, reg_addr, base_high);
112 bar_cnt--;
113 reg_addr += 4;
114 is_64 = 1;
115 }
116
117 base = base | ((u64)base_high << 32);
118 size = size | ((u64)size_high << 32);
119
120 if ((!is_64 && size_low) || (is_64 && size)) {
121 size = ~size + 1;
122 printf(" %d %#018llx %#018llx %d %s %s\n",
123 bar_id, (unsigned long long)base,
124 (unsigned long long)size, is_64 ? 64 : 32,
125 is_io ? "I/O" : "MEM",
126 prefetchable ? "Prefetchable" : "");
127 }
128
129 bar_id++;
130 bar_cnt--;
131 }
132
133 return 0;
134 }
135
136 static struct pci_reg_info regs_start[] = {
137 { "vendor ID", PCI_SIZE_16, PCI_VENDOR_ID },
138 { "device ID", PCI_SIZE_16, PCI_DEVICE_ID },
139 { "command register ID", PCI_SIZE_16, PCI_COMMAND },
140 { "status register", PCI_SIZE_16, PCI_STATUS },
141 { "revision ID", PCI_SIZE_8, PCI_REVISION_ID },
142 {},
143 };
144
145 static struct pci_reg_info regs_rest[] = {
146 { "sub class code", PCI_SIZE_8, PCI_CLASS_SUB_CODE },
147 { "programming interface", PCI_SIZE_8, PCI_CLASS_PROG },
148 { "cache line", PCI_SIZE_8, PCI_CACHE_LINE_SIZE },
149 { "latency time", PCI_SIZE_8, PCI_LATENCY_TIMER },
150 { "header type", PCI_SIZE_8, PCI_HEADER_TYPE },
151 { "BIST", PCI_SIZE_8, PCI_BIST },
152 { "base address 0", PCI_SIZE_32, PCI_BASE_ADDRESS_0 },
153 {},
154 };
155
156 static struct pci_reg_info regs_normal[] = {
157 { "base address 1", PCI_SIZE_32, PCI_BASE_ADDRESS_1 },
158 { "base address 2", PCI_SIZE_32, PCI_BASE_ADDRESS_2 },
159 { "base address 3", PCI_SIZE_32, PCI_BASE_ADDRESS_3 },
160 { "base address 4", PCI_SIZE_32, PCI_BASE_ADDRESS_4 },
161 { "base address 5", PCI_SIZE_32, PCI_BASE_ADDRESS_5 },
162 { "cardBus CIS pointer", PCI_SIZE_32, PCI_CARDBUS_CIS },
163 { "sub system vendor ID", PCI_SIZE_16, PCI_SUBSYSTEM_VENDOR_ID },
164 { "sub system ID", PCI_SIZE_16, PCI_SUBSYSTEM_ID },
165 { "expansion ROM base address", PCI_SIZE_32, PCI_ROM_ADDRESS },
166 { "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
167 { "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
168 { "min Grant", PCI_SIZE_8, PCI_MIN_GNT },
169 { "max Latency", PCI_SIZE_8, PCI_MAX_LAT },
170 {},
171 };
172
173 static struct pci_reg_info regs_bridge[] = {
174 { "base address 1", PCI_SIZE_32, PCI_BASE_ADDRESS_1 },
175 { "primary bus number", PCI_SIZE_8, PCI_PRIMARY_BUS },
176 { "secondary bus number", PCI_SIZE_8, PCI_SECONDARY_BUS },
177 { "subordinate bus number", PCI_SIZE_8, PCI_SUBORDINATE_BUS },
178 { "secondary latency timer", PCI_SIZE_8, PCI_SEC_LATENCY_TIMER },
179 { "IO base", PCI_SIZE_8, PCI_IO_BASE },
180 { "IO limit", PCI_SIZE_8, PCI_IO_LIMIT },
181 { "secondary status", PCI_SIZE_16, PCI_SEC_STATUS },
182 { "memory base", PCI_SIZE_16, PCI_MEMORY_BASE },
183 { "memory limit", PCI_SIZE_16, PCI_MEMORY_LIMIT },
184 { "prefetch memory base", PCI_SIZE_16, PCI_PREF_MEMORY_BASE },
185 { "prefetch memory limit", PCI_SIZE_16, PCI_PREF_MEMORY_LIMIT },
186 { "prefetch memory base upper", PCI_SIZE_32, PCI_PREF_BASE_UPPER32 },
187 { "prefetch memory limit upper", PCI_SIZE_32, PCI_PREF_LIMIT_UPPER32 },
188 { "IO base upper 16 bits", PCI_SIZE_16, PCI_IO_BASE_UPPER16 },
189 { "IO limit upper 16 bits", PCI_SIZE_16, PCI_IO_LIMIT_UPPER16 },
190 { "expansion ROM base address", PCI_SIZE_32, PCI_ROM_ADDRESS1 },
191 { "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
192 { "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
193 { "bridge control", PCI_SIZE_16, PCI_BRIDGE_CONTROL },
194 {},
195 };
196
197 static struct pci_reg_info regs_cardbus[] = {
198 { "capabilities", PCI_SIZE_8, PCI_CB_CAPABILITY_LIST },
199 { "secondary status", PCI_SIZE_16, PCI_CB_SEC_STATUS },
200 { "primary bus number", PCI_SIZE_8, PCI_CB_PRIMARY_BUS },
201 { "CardBus number", PCI_SIZE_8, PCI_CB_CARD_BUS },
202 { "subordinate bus number", PCI_SIZE_8, PCI_CB_SUBORDINATE_BUS },
203 { "CardBus latency timer", PCI_SIZE_8, PCI_CB_LATENCY_TIMER },
204 { "CardBus memory base 0", PCI_SIZE_32, PCI_CB_MEMORY_BASE_0 },
205 { "CardBus memory limit 0", PCI_SIZE_32, PCI_CB_MEMORY_LIMIT_0 },
206 { "CardBus memory base 1", PCI_SIZE_32, PCI_CB_MEMORY_BASE_1 },
207 { "CardBus memory limit 1", PCI_SIZE_32, PCI_CB_MEMORY_LIMIT_1 },
208 { "CardBus IO base 0", PCI_SIZE_16, PCI_CB_IO_BASE_0 },
209 { "CardBus IO base high 0", PCI_SIZE_16, PCI_CB_IO_BASE_0_HI },
210 { "CardBus IO limit 0", PCI_SIZE_16, PCI_CB_IO_LIMIT_0 },
211 { "CardBus IO limit high 0", PCI_SIZE_16, PCI_CB_IO_LIMIT_0_HI },
212 { "CardBus IO base 1", PCI_SIZE_16, PCI_CB_IO_BASE_1 },
213 { "CardBus IO base high 1", PCI_SIZE_16, PCI_CB_IO_BASE_1_HI },
214 { "CardBus IO limit 1", PCI_SIZE_16, PCI_CB_IO_LIMIT_1 },
215 { "CardBus IO limit high 1", PCI_SIZE_16, PCI_CB_IO_LIMIT_1_HI },
216 { "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
217 { "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
218 { "bridge control", PCI_SIZE_16, PCI_CB_BRIDGE_CONTROL },
219 { "subvendor ID", PCI_SIZE_16, PCI_CB_SUBSYSTEM_VENDOR_ID },
220 { "subdevice ID", PCI_SIZE_16, PCI_CB_SUBSYSTEM_ID },
221 { "PC Card 16bit base address", PCI_SIZE_32, PCI_CB_LEGACY_MODE_BASE },
222 {},
223 };
224
225 /**
226 * pci_header_show() - Show the header of the specified PCI device.
227 *
228 * @dev: Bus+Device+Function number
229 */
pci_header_show(struct udevice * dev)230 static void pci_header_show(struct udevice *dev)
231 {
232 unsigned long class, header_type;
233
234 dm_pci_read_config(dev, PCI_CLASS_CODE, &class, PCI_SIZE_8);
235 dm_pci_read_config(dev, PCI_HEADER_TYPE, &header_type, PCI_SIZE_8);
236 pci_show_regs(dev, regs_start);
237 printf(" class code = 0x%.2x (%s)\n", (int)class,
238 pci_class_str(class));
239 pci_show_regs(dev, regs_rest);
240
241 switch (header_type & 0x7f) {
242 case PCI_HEADER_TYPE_NORMAL: /* "normal" PCI device */
243 pci_show_regs(dev, regs_normal);
244 break;
245 case PCI_HEADER_TYPE_BRIDGE: /* PCI-to-PCI bridge */
246 pci_show_regs(dev, regs_bridge);
247 break;
248 case PCI_HEADER_TYPE_CARDBUS: /* PCI-to-CardBus bridge */
249 pci_show_regs(dev, regs_cardbus);
250 break;
251
252 default:
253 printf("unknown header\n");
254 break;
255 }
256 }
257
pciinfo_header(bool short_listing)258 static void pciinfo_header(bool short_listing)
259 {
260 if (short_listing) {
261 printf("BusDevFun VendorId DeviceId Device Class Sub-Class\n");
262 printf("_____________________________________________________________\n");
263 }
264 }
265
266 /**
267 * pci_header_show_brief() - Show the short-form PCI device header
268 *
269 * Reads and prints the header of the specified PCI device in short form.
270 *
271 * @dev: PCI device to show
272 */
pci_header_show_brief(struct udevice * dev)273 static void pci_header_show_brief(struct udevice *dev)
274 {
275 ulong vendor, device;
276 ulong class, subclass;
277
278 dm_pci_read_config(dev, PCI_VENDOR_ID, &vendor, PCI_SIZE_16);
279 dm_pci_read_config(dev, PCI_DEVICE_ID, &device, PCI_SIZE_16);
280 dm_pci_read_config(dev, PCI_CLASS_CODE, &class, PCI_SIZE_8);
281 dm_pci_read_config(dev, PCI_CLASS_SUB_CODE, &subclass, PCI_SIZE_8);
282
283 printf("0x%.4lx 0x%.4lx %-23s 0x%.2lx\n",
284 vendor, device,
285 pci_class_str(class), subclass);
286 }
287
pciinfo(struct udevice * bus,bool short_listing,bool multi)288 static void pciinfo(struct udevice *bus, bool short_listing, bool multi)
289 {
290 struct udevice *dev;
291
292 if (!multi)
293 printf("Scanning PCI devices on bus %d\n", dev_seq(bus));
294
295 if (!multi || dev_seq(bus) == 0)
296 pciinfo_header(short_listing);
297
298 for (device_find_first_child(bus, &dev);
299 dev;
300 device_find_next_child(&dev)) {
301 struct pci_child_plat *pplat;
302
303 pplat = dev_get_parent_plat(dev);
304 if (short_listing) {
305 printf("%02x.%02x.%02x ", dev_seq(bus),
306 PCI_DEV(pplat->devfn), PCI_FUNC(pplat->devfn));
307 pci_header_show_brief(dev);
308 } else {
309 printf("\nFound PCI device %02x.%02x.%02x:\n",
310 dev_seq(bus),
311 PCI_DEV(pplat->devfn), PCI_FUNC(pplat->devfn));
312 pci_header_show(dev);
313 }
314 }
315 }
316
317 /**
318 * get_pci_dev() - Convert the "bus.device.function" identifier into a number
319 *
320 * @name: Device string in the form "bus.device.function" where each is in hex
321 * Return: encoded pci_dev_t or -1 if the string was invalid
322 */
get_pci_dev(char * name)323 static pci_dev_t get_pci_dev(char *name)
324 {
325 char cnum[12];
326 int len, i, iold, n;
327 int bdfs[3] = {0,0,0};
328
329 len = strlen(name);
330 if (len > 8)
331 return -1;
332 for (i = 0, iold = 0, n = 0; i < len; i++) {
333 if (name[i] == '.') {
334 memcpy(cnum, &name[iold], i - iold);
335 cnum[i - iold] = '\0';
336 bdfs[n++] = hextoul(cnum, NULL);
337 iold = i + 1;
338 }
339 }
340 strcpy(cnum, &name[iold]);
341 if (n == 0)
342 n = 1;
343 bdfs[n] = hextoul(cnum, NULL);
344
345 return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]);
346 }
347
pci_cfg_display(struct udevice * dev,ulong addr,enum pci_size_t size,ulong length)348 static int pci_cfg_display(struct udevice *dev, ulong addr,
349 enum pci_size_t size, ulong length)
350 {
351 #define DISP_LINE_LEN 16
352 ulong i, nbytes, linebytes;
353 int byte_size;
354 int rc = 0;
355
356 byte_size = pci_byte_size(size);
357 if (length == 0)
358 length = 0x40 / byte_size; /* Standard PCI config space */
359
360 if (addr >= 4096)
361 return 1;
362
363 /* Print the lines.
364 * once, and all accesses are with the specified bus width.
365 */
366 nbytes = length * byte_size;
367 do {
368 printf("%08lx:", addr);
369 linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
370 for (i = 0; i < linebytes; i += byte_size) {
371 unsigned long val;
372
373 dm_pci_read_config(dev, addr, &val, size);
374 printf(" %0*lx", pci_field_width(size), val);
375 addr += byte_size;
376 }
377 printf("\n");
378 nbytes -= linebytes;
379 if (ctrlc()) {
380 rc = 1;
381 break;
382 }
383 } while (nbytes > 0 && addr < 4096);
384
385 if (rc == 0 && nbytes > 0)
386 return 1;
387
388 return (rc);
389 }
390
pci_cfg_modify(struct udevice * dev,ulong addr,ulong size,ulong value,int incrflag)391 static int pci_cfg_modify(struct udevice *dev, ulong addr, ulong size,
392 ulong value, int incrflag)
393 {
394 ulong i;
395 int nbytes;
396 ulong val;
397
398 if (addr >= 4096)
399 return 1;
400
401 /* Print the address, followed by value. Then accept input for
402 * the next value. A non-converted value exits.
403 */
404 do {
405 printf("%08lx:", addr);
406 dm_pci_read_config(dev, addr, &val, size);
407 printf(" %0*lx", pci_field_width(size), val);
408
409 nbytes = cli_readline(" ? ");
410 if (nbytes == 0 || (nbytes == 1 && console_buffer[0] == '-')) {
411 /* <CR> pressed as only input, don't modify current
412 * location and move to next. "-" pressed will go back.
413 */
414 if (incrflag)
415 addr += nbytes ? -size : size;
416 nbytes = 1;
417 /* good enough to not time out */
418 bootretry_reset_cmd_timeout();
419 }
420 #ifdef CONFIG_BOOT_RETRY_TIME
421 else if (nbytes == -2) {
422 break; /* timed out, exit the command */
423 }
424 #endif
425 else {
426 char *endp;
427 i = hextoul(console_buffer, &endp);
428 nbytes = endp - console_buffer;
429 if (nbytes) {
430 /* good enough to not time out
431 */
432 bootretry_reset_cmd_timeout();
433 dm_pci_write_config(dev, addr, i, size);
434 if (incrflag)
435 addr += size;
436 }
437 }
438 } while (nbytes && addr < 4096);
439
440 if (nbytes)
441 return 1;
442
443 return 0;
444 }
445
446 static const struct pci_flag_info {
447 uint flag;
448 const char *name;
449 } pci_flag_info[] = {
450 { PCI_REGION_IO, "io" },
451 { PCI_REGION_PREFETCH, "prefetch" },
452 { PCI_REGION_SYS_MEMORY, "sysmem" },
453 { PCI_REGION_RO, "readonly" },
454 };
455
pci_show_regions(struct udevice * bus)456 static void pci_show_regions(struct udevice *bus)
457 {
458 struct pci_controller *hose = dev_get_uclass_priv(pci_get_controller(bus));
459 const struct pci_region *reg;
460 int i, j;
461
462 if (!hose) {
463 printf("Bus '%s' is not a PCI controller\n", bus->name);
464 return;
465 }
466
467 printf("Buses %02x-%02x\n", hose->first_busno, hose->last_busno);
468 printf("# %-18s %-18s %-18s %s\n", "Bus start", "Phys start", "Size",
469 "Flags");
470 for (i = 0, reg = hose->regions; i < hose->region_count; i++, reg++) {
471 printf("%d %#018llx %#018llx %#018llx ", i,
472 (unsigned long long)reg->bus_start,
473 (unsigned long long)reg->phys_start,
474 (unsigned long long)reg->size);
475 if (!(reg->flags & PCI_REGION_TYPE))
476 printf("mem ");
477 for (j = 0; j < ARRAY_SIZE(pci_flag_info); j++) {
478 if (reg->flags & pci_flag_info[j].flag)
479 printf("%s ", pci_flag_info[j].name);
480 }
481 printf("\n");
482 }
483 }
484
485 /* PCI Configuration Space access commands
486 *
487 * Syntax:
488 * pci display[.b, .w, .l] bus.device.function} [addr] [len]
489 * pci next[.b, .w, .l] bus.device.function [addr]
490 * pci modify[.b, .w, .l] bus.device.function [addr]
491 * pci write[.b, .w, .l] bus.device.function addr value
492 */
do_pci(struct cmd_tbl * cmdtp,int flag,int argc,char * const argv[])493 static int do_pci(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
494 {
495 ulong addr = 0, value = 0, cmd_size = 0;
496 enum pci_size_t size = PCI_SIZE_32;
497 struct udevice *dev, *bus;
498 int busnum = -1;
499 pci_dev_t bdf = 0;
500 char cmd = 's';
501 int ret = 0;
502 char *endp;
503
504 if (argc > 1)
505 cmd = argv[1][0];
506
507 switch (cmd) {
508 case 'd': /* display */
509 case 'n': /* next */
510 case 'm': /* modify */
511 case 'w': /* write */
512 /* Check for a size specification. */
513 cmd_size = cmd_get_data_size(argv[1], 4);
514 size = (cmd_size == 4) ? PCI_SIZE_32 : cmd_size - 1;
515 if (argc > 3)
516 addr = hextoul(argv[3], NULL);
517 if (argc > 4)
518 value = hextoul(argv[4], NULL);
519 fallthrough;
520 case 'h': /* header */
521 case 'b': /* bars */
522 if (argc < 3)
523 goto usage;
524 if ((bdf = get_pci_dev(argv[2])) == -1)
525 return 1;
526 break;
527 case 'e':
528 pci_init();
529 return 0;
530 case 'r': /* no break */
531 default: /* scan bus */
532 value = 1; /* short listing */
533 if (argc > 1) {
534 if (cmd != 'r' && argv[argc-1][0] == 'l') {
535 value = 0;
536 argc--;
537 }
538 if (argc > 2 || (argc > 1 && cmd != 'r' && argv[1][0] != 's')) {
539 if (argv[argc - 1][0] != '*') {
540 busnum = hextoul(argv[argc - 1], &endp);
541 if (*endp)
542 goto usage;
543 }
544 argc--;
545 }
546 if (cmd == 'r' && argc > 2)
547 goto usage;
548 else if (cmd != 'r' && (argc > 2 || (argc == 2 && argv[1][0] != 's')))
549 goto usage;
550 }
551 if (busnum == -1) {
552 if (cmd != 'r') {
553 for (busnum = 0;
554 uclass_get_device_by_seq(UCLASS_PCI, busnum, &bus) == 0;
555 busnum++)
556 pciinfo(bus, value, true);
557 } else {
558 for (busnum = 0;
559 uclass_get_device_by_seq(UCLASS_PCI, busnum, &bus) == 0;
560 busnum++) {
561 /* Regions are controller specific so skip non-root buses */
562 if (device_is_on_pci_bus(bus))
563 continue;
564 pci_show_regions(bus);
565 }
566 }
567 return 0;
568 }
569 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, &bus);
570 if (ret) {
571 printf("No such bus\n");
572 return CMD_RET_FAILURE;
573 }
574 if (cmd == 'r')
575 pci_show_regions(bus);
576 else
577 pciinfo(bus, value, false);
578 return 0;
579 }
580
581 ret = dm_pci_bus_find_bdf(bdf, &dev);
582 if (ret) {
583 printf("No such device\n");
584 return CMD_RET_FAILURE;
585 }
586
587 switch (argv[1][0]) {
588 case 'h': /* header */
589 pci_header_show(dev);
590 break;
591 case 'd': /* display */
592 return pci_cfg_display(dev, addr, size, value);
593 case 'n': /* next */
594 if (argc < 4)
595 goto usage;
596 ret = pci_cfg_modify(dev, addr, size, value, 0);
597 break;
598 case 'm': /* modify */
599 if (argc < 4)
600 goto usage;
601 ret = pci_cfg_modify(dev, addr, size, value, 1);
602 break;
603 case 'w': /* write */
604 if (argc < 5)
605 goto usage;
606 ret = dm_pci_write_config(dev, addr, value, size);
607 break;
608 case 'b': /* bars */
609 return pci_bar_show(dev);
610 default:
611 ret = CMD_RET_USAGE;
612 break;
613 }
614
615 return ret;
616 usage:
617 return CMD_RET_USAGE;
618 }
619
620 /***************************************************/
621
622 U_BOOT_LONGHELP(pci,
623 "[bus|*] [long]\n"
624 " - short or long list of PCI devices on bus 'bus'\n"
625 "pci enum\n"
626 " - Enumerate PCI buses\n"
627 "pci header b.d.f\n"
628 " - show header of PCI device 'bus.device.function'\n"
629 "pci bar b.d.f\n"
630 " - show BARs base and size for device b.d.f'\n"
631 "pci regions [bus|*]\n"
632 " - show PCI regions\n"
633 "pci display[.b, .w, .l] b.d.f [address] [# of objects]\n"
634 " - display PCI configuration space (CFG)\n"
635 "pci next[.b, .w, .l] b.d.f address\n"
636 " - modify, read and keep CFG address\n"
637 "pci modify[.b, .w, .l] b.d.f address\n"
638 " - modify, auto increment CFG address\n"
639 "pci write[.b, .w, .l] b.d.f address value\n"
640 " - write to CFG address");
641
642 U_BOOT_CMD(
643 pci, 5, 1, do_pci,
644 "list and access PCI Configuration Space", pci_help_text
645 );
646