1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2011 Freescale Semiconductor, Inc.
4 * Copyright 2019 NXP
5 * Author: Tang Yuantian <b29983@freescale.com>
6 */
7
8 #include <blk.h>
9 #include <cpu_func.h>
10 #include <dm.h>
11 #include <log.h>
12 #include <pci.h>
13 #include <command.h>
14 #include <asm/byteorder.h>
15 #include <malloc.h>
16 #include <asm/io.h>
17 #include <fis.h>
18 #include <sata.h>
19 #include <libata.h>
20 #include <sata.h>
21 #include <dm/device-internal.h>
22 #include <linux/delay.h>
23
24 #include "sata_sil.h"
25
26 #define virt_to_bus(devno, v) dm_pci_virt_to_mem(devno, (void *) (v))
27
28 /* just compatible ahci_ops */
29 struct sil_ops {
30 int *rev0;
31 int *rev1;
32 int (*scan)(struct udevice *dev);
33 };
34
35 static struct sata_info sata_info;
36
37 static struct pci_device_id supported[] = {
38 { PCI_DEVICE(PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3131) },
39 { PCI_DEVICE(PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3132) },
40 { PCI_DEVICE(PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3124) },
41 {}
42 };
43
sil_sata_dump_fis(struct sata_fis_d2h * s)44 static void sil_sata_dump_fis(struct sata_fis_d2h *s)
45 {
46 printf("Status FIS dump:\n");
47 printf("fis_type: %02x\n", s->fis_type);
48 printf("pm_port_i: %02x\n", s->pm_port_i);
49 printf("status: %02x\n", s->status);
50 printf("error: %02x\n", s->error);
51 printf("lba_low: %02x\n", s->lba_low);
52 printf("lba_mid: %02x\n", s->lba_mid);
53 printf("lba_high: %02x\n", s->lba_high);
54 printf("device: %02x\n", s->device);
55 printf("lba_low_exp: %02x\n", s->lba_low_exp);
56 printf("lba_mid_exp: %02x\n", s->lba_mid_exp);
57 printf("lba_high_exp: %02x\n", s->lba_high_exp);
58 printf("res1: %02x\n", s->res1);
59 printf("sector_count: %02x\n", s->sector_count);
60 printf("sector_count_exp: %02x\n", s->sector_count_exp);
61 }
62
sata_spd_string(unsigned int speed)63 static const char *sata_spd_string(unsigned int speed)
64 {
65 static const char * const spd_str[] = {
66 "1.5 Gbps",
67 "3.0 Gbps",
68 "6.0 Gbps",
69 };
70
71 if ((speed - 1) > 2)
72 return "<unknown>";
73
74 return spd_str[speed - 1];
75 }
76
ata_wait_register(void * reg,u32 mask,u32 val,int timeout_msec)77 static u32 ata_wait_register(void *reg, u32 mask,
78 u32 val, int timeout_msec)
79 {
80 u32 tmp;
81
82 tmp = readl(reg);
83 while ((tmp & mask) == val && timeout_msec > 0) {
84 mdelay(1);
85 timeout_msec--;
86 tmp = readl(reg);
87 }
88
89 return tmp;
90 }
91
sil_config_port(void * port)92 static void sil_config_port(void *port)
93 {
94 /* configure IRQ WoC */
95 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
96
97 /* zero error counters. */
98 writew(0x8000, port + PORT_DECODE_ERR_THRESH);
99 writew(0x8000, port + PORT_CRC_ERR_THRESH);
100 writew(0x8000, port + PORT_HSHK_ERR_THRESH);
101 writew(0x0000, port + PORT_DECODE_ERR_CNT);
102 writew(0x0000, port + PORT_CRC_ERR_CNT);
103 writew(0x0000, port + PORT_HSHK_ERR_CNT);
104
105 /* always use 64bit activation */
106 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
107
108 /* clear port multiplier enable and resume bits */
109 writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
110 }
111
sil_init_port(void * port)112 static int sil_init_port(void *port)
113 {
114 u32 tmp;
115
116 writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
117 ata_wait_register(port + PORT_CTRL_STAT,
118 PORT_CS_INIT, PORT_CS_INIT, 100);
119 tmp = ata_wait_register(port + PORT_CTRL_STAT,
120 PORT_CS_RDY, 0, 100);
121
122 if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY)
123 return 1;
124
125 return 0;
126 }
127
sil_read_fis(struct sil_sata * sata,int tag,struct sata_fis_d2h * fis)128 static void sil_read_fis(struct sil_sata *sata, int tag,
129 struct sata_fis_d2h *fis)
130 {
131 void *port = sata->port;
132 struct sil_prb *prb;
133 int i;
134 u32 *src, *dst;
135
136 prb = port + PORT_LRAM + tag * PORT_LRAM_SLOT_SZ;
137 src = (u32 *)&prb->fis;
138 dst = (u32 *)fis;
139 for (i = 0; i < sizeof(struct sata_fis_h2d); i += 4)
140 *dst++ = readl(src++);
141 }
142
sil_exec_cmd(struct sil_sata * sata,struct sil_cmd_block * pcmd,int tag)143 static int sil_exec_cmd(struct sil_sata *sata, struct sil_cmd_block *pcmd,
144 int tag)
145 {
146 void *port = sata->port;
147 u64 paddr = virt_to_bus(sata->devno, pcmd);
148 u32 irq_mask, irq_stat;
149 int rc;
150
151 writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR);
152
153 /* better to add momery barrior here */
154 writel((u32)paddr, port + PORT_CMD_ACTIVATE + tag * 8);
155 writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + tag * 8 + 4);
156
157 irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
158 irq_stat = ata_wait_register(port + PORT_IRQ_STAT, irq_mask,
159 0, 10000);
160
161 /* clear IRQs */
162 writel(irq_mask, port + PORT_IRQ_STAT);
163 irq_stat >>= PORT_IRQ_RAW_SHIFT;
164
165 if (irq_stat & PORT_IRQ_COMPLETE)
166 rc = 0;
167 else {
168 /* force port into known state */
169 sil_init_port(port);
170 if (irq_stat & PORT_IRQ_ERROR)
171 rc = 1; /* error */
172 else
173 rc = 2; /* busy */
174 }
175
176 return rc;
177 }
178
sil_cmd_set_feature(struct sil_sata * sata)179 static int sil_cmd_set_feature(struct sil_sata *sata)
180 {
181 struct sil_cmd_block cmdb, *pcmd = &cmdb;
182 struct sata_fis_d2h fis;
183 u8 udma_cap;
184 int ret;
185
186 memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));
187 pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
188 pcmd->prb.fis.pm_port_c = (1 << 7);
189 pcmd->prb.fis.command = ATA_CMD_SET_FEATURES;
190 pcmd->prb.fis.features = SETFEATURES_XFER;
191
192 /* First check the device capablity */
193 udma_cap = (u8)(sata->udma & 0xff);
194 debug("udma_cap %02x\n", udma_cap);
195
196 if (udma_cap == ATA_UDMA6)
197 pcmd->prb.fis.sector_count = XFER_UDMA_6;
198 if (udma_cap == ATA_UDMA5)
199 pcmd->prb.fis.sector_count = XFER_UDMA_5;
200 if (udma_cap == ATA_UDMA4)
201 pcmd->prb.fis.sector_count = XFER_UDMA_4;
202 if (udma_cap == ATA_UDMA3)
203 pcmd->prb.fis.sector_count = XFER_UDMA_3;
204
205 ret = sil_exec_cmd(sata, pcmd, 0);
206 if (ret) {
207 sil_read_fis(sata, 0, &fis);
208 printf("Err: exe cmd(0x%x).\n",
209 readl(sata->port + PORT_SERROR));
210 sil_sata_dump_fis(&fis);
211 return 1;
212 }
213
214 return 0;
215 }
216
sil_sata_init_wcache(struct sil_sata * sata,u16 * id)217 static void sil_sata_init_wcache(struct sil_sata *sata, u16 *id)
218 {
219 if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
220 sata->wcache = 1;
221 if (ata_id_has_flush(id))
222 sata->flush = 1;
223 if (ata_id_has_flush_ext(id))
224 sata->flush_ext = 1;
225 }
226
sil_sata_set_feature_by_id(struct sil_sata * sata,u16 * id)227 static void sil_sata_set_feature_by_id(struct sil_sata *sata, u16 *id)
228 {
229 #ifdef CONFIG_LBA48
230 /* Check if support LBA48 */
231 if (ata_id_has_lba48(id)) {
232 sata->lba48 = 1;
233 debug("Device supports LBA48\n");
234 } else {
235 debug("Device supports LBA28\n");
236 }
237 #endif
238
239 sil_sata_init_wcache(sata, id);
240 sil_cmd_set_feature(sata);
241 }
242
sil_cmd_identify_device(struct sil_sata * sata,u16 * id)243 static int sil_cmd_identify_device(struct sil_sata *sata, u16 *id)
244 {
245 struct sil_cmd_block cmdb, *pcmd = &cmdb;
246 struct sata_fis_d2h fis;
247 int ret;
248
249 memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));
250 pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
251 pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
252 pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
253 pcmd->prb.fis.pm_port_c = (1 << 7);
254 pcmd->prb.fis.command = ATA_CMD_ID_ATA;
255 pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, id));
256 pcmd->sge.cnt = cpu_to_le32(sizeof(id[0]) * ATA_ID_WORDS);
257 pcmd->sge.flags = cpu_to_le32(SGE_TRM);
258
259 ret = sil_exec_cmd(sata, pcmd, 0);
260 if (ret) {
261 sil_read_fis(sata, 0, &fis);
262 printf("Err: id cmd(0x%x).\n", readl(sata->port + PORT_SERROR));
263 sil_sata_dump_fis(&fis);
264 return 1;
265 }
266 ata_swap_buf_le16(id, ATA_ID_WORDS);
267
268 return 0;
269 }
270
sil_cmd_soft_reset(struct sil_sata * sata)271 static int sil_cmd_soft_reset(struct sil_sata *sata)
272 {
273 struct sil_cmd_block cmdb, *pcmd = &cmdb;
274 struct sata_fis_d2h fis;
275 void *port = sata->port;
276 int ret;
277
278 /* put the port into known state */
279 if (sil_init_port(port)) {
280 printf("SRST: port %d not ready\n", sata->id);
281 return 1;
282 }
283
284 memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));
285
286 pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_SRST);
287 pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
288 pcmd->prb.fis.pm_port_c = 0xf;
289
290 ret = sil_exec_cmd(sata, &cmdb, 0);
291 if (ret) {
292 sil_read_fis(sata, 0, &fis);
293 printf("SRST cmd error.\n");
294 sil_sata_dump_fis(&fis);
295 return 1;
296 }
297
298 return 0;
299 }
300
sil_sata_rw_cmd(struct sil_sata * sata,ulong start,ulong blkcnt,u8 * buffer,int is_write)301 static ulong sil_sata_rw_cmd(struct sil_sata *sata, ulong start, ulong blkcnt,
302 u8 *buffer, int is_write)
303 {
304 struct sil_cmd_block cmdb, *pcmd = &cmdb;
305 struct sata_fis_d2h fis;
306 u64 block;
307 int ret;
308
309 block = (u64)start;
310 memset(pcmd, 0, sizeof(struct sil_cmd_block));
311 pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
312 pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
313 pcmd->prb.fis.pm_port_c = (1 << 7);
314 if (is_write) {
315 pcmd->prb.fis.command = ATA_CMD_WRITE;
316 pcmd->prb.prot = cpu_to_le16(PRB_PROT_WRITE);
317 } else {
318 pcmd->prb.fis.command = ATA_CMD_READ;
319 pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
320 }
321
322 pcmd->prb.fis.device = ATA_LBA;
323 pcmd->prb.fis.device |= (block >> 24) & 0xf;
324 pcmd->prb.fis.lba_high = (block >> 16) & 0xff;
325 pcmd->prb.fis.lba_mid = (block >> 8) & 0xff;
326 pcmd->prb.fis.lba_low = block & 0xff;
327 pcmd->prb.fis.sector_count = (u8)blkcnt & 0xff;
328
329 pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, buffer));
330 pcmd->sge.cnt = cpu_to_le32(blkcnt * ATA_SECT_SIZE);
331 pcmd->sge.flags = cpu_to_le32(SGE_TRM);
332
333 ret = sil_exec_cmd(sata, pcmd, 0);
334 if (ret) {
335 sil_read_fis(sata, 0, &fis);
336 printf("Err: rw cmd(0x%08x).\n",
337 readl(sata->port + PORT_SERROR));
338 sil_sata_dump_fis(&fis);
339 return 1;
340 }
341
342 return blkcnt;
343 }
344
sil_sata_rw_cmd_ext(struct sil_sata * sata,ulong start,ulong blkcnt,u8 * buffer,int is_write)345 static ulong sil_sata_rw_cmd_ext(struct sil_sata *sata, ulong start,
346 ulong blkcnt, u8 *buffer, int is_write)
347 {
348 struct sil_cmd_block cmdb, *pcmd = &cmdb;
349 struct sata_fis_d2h fis;
350 u64 block;
351 int ret;
352
353 block = (u64)start;
354 memset(pcmd, 0, sizeof(struct sil_cmd_block));
355 pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
356 pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
357 pcmd->prb.fis.pm_port_c = (1 << 7);
358 if (is_write) {
359 pcmd->prb.fis.command = ATA_CMD_WRITE_EXT;
360 pcmd->prb.prot = cpu_to_le16(PRB_PROT_WRITE);
361 } else {
362 pcmd->prb.fis.command = ATA_CMD_READ_EXT;
363 pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
364 }
365
366 pcmd->prb.fis.lba_high_exp = (block >> 40) & 0xff;
367 pcmd->prb.fis.lba_mid_exp = (block >> 32) & 0xff;
368 pcmd->prb.fis.lba_low_exp = (block >> 24) & 0xff;
369 pcmd->prb.fis.lba_high = (block >> 16) & 0xff;
370 pcmd->prb.fis.lba_mid = (block >> 8) & 0xff;
371 pcmd->prb.fis.lba_low = block & 0xff;
372 pcmd->prb.fis.device = ATA_LBA;
373 pcmd->prb.fis.sector_count_exp = (blkcnt >> 8) & 0xff;
374 pcmd->prb.fis.sector_count = blkcnt & 0xff;
375
376 pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, buffer));
377 pcmd->sge.cnt = cpu_to_le32(blkcnt * ATA_SECT_SIZE);
378 pcmd->sge.flags = cpu_to_le32(SGE_TRM);
379
380 ret = sil_exec_cmd(sata, pcmd, 0);
381 if (ret) {
382 sil_read_fis(sata, 0, &fis);
383 printf("Err: rw ext cmd(0x%08x).\n",
384 readl(sata->port + PORT_SERROR));
385 sil_sata_dump_fis(&fis);
386 return 1;
387 }
388
389 return blkcnt;
390 }
391
sil_sata_rw_lba28(struct sil_sata * sata,ulong blknr,lbaint_t blkcnt,const void * buffer,int is_write)392 static ulong sil_sata_rw_lba28(struct sil_sata *sata, ulong blknr,
393 lbaint_t blkcnt, const void *buffer,
394 int is_write)
395 {
396 ulong start, blks, max_blks;
397 u8 *addr;
398
399 start = blknr;
400 blks = blkcnt;
401 addr = (u8 *)buffer;
402
403 max_blks = ATA_MAX_SECTORS;
404 do {
405 if (blks > max_blks) {
406 sil_sata_rw_cmd(sata, start, max_blks, addr, is_write);
407 start += max_blks;
408 blks -= max_blks;
409 addr += ATA_SECT_SIZE * max_blks;
410 } else {
411 sil_sata_rw_cmd(sata, start, blks, addr, is_write);
412 start += blks;
413 blks = 0;
414 addr += ATA_SECT_SIZE * blks;
415 }
416 } while (blks != 0);
417
418 return blkcnt;
419 }
420
sil_sata_rw_lba48(struct sil_sata * sata,ulong blknr,lbaint_t blkcnt,const void * buffer,int is_write)421 static ulong sil_sata_rw_lba48(struct sil_sata *sata, ulong blknr,
422 lbaint_t blkcnt, const void *buffer,
423 int is_write)
424 {
425 ulong start, blks, max_blks;
426 u8 *addr;
427
428 start = blknr;
429 blks = blkcnt;
430 addr = (u8 *)buffer;
431
432 max_blks = ATA_MAX_SECTORS_LBA48;
433 do {
434 if (blks > max_blks) {
435 sil_sata_rw_cmd_ext(sata, start, max_blks,
436 addr, is_write);
437 start += max_blks;
438 blks -= max_blks;
439 addr += ATA_SECT_SIZE * max_blks;
440 } else {
441 sil_sata_rw_cmd_ext(sata, start, blks,
442 addr, is_write);
443 start += blks;
444 blks = 0;
445 addr += ATA_SECT_SIZE * blks;
446 }
447 } while (blks != 0);
448
449 return blkcnt;
450 }
451
sil_sata_cmd_flush_cache(struct sil_sata * sata)452 static void sil_sata_cmd_flush_cache(struct sil_sata *sata)
453 {
454 struct sil_cmd_block cmdb, *pcmd = &cmdb;
455
456 memset((void *)pcmd, 0, sizeof(struct sil_cmd_block));
457 pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
458 pcmd->prb.fis.pm_port_c = (1 << 7);
459 pcmd->prb.fis.command = ATA_CMD_FLUSH;
460
461 sil_exec_cmd(sata, pcmd, 0);
462 }
463
sil_sata_cmd_flush_cache_ext(struct sil_sata * sata)464 static void sil_sata_cmd_flush_cache_ext(struct sil_sata *sata)
465 {
466 struct sil_cmd_block cmdb, *pcmd = &cmdb;
467
468 memset((void *)pcmd, 0, sizeof(struct sil_cmd_block));
469 pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
470 pcmd->prb.fis.pm_port_c = (1 << 7);
471 pcmd->prb.fis.command = ATA_CMD_FLUSH_EXT;
472
473 sil_exec_cmd(sata, pcmd, 0);
474 }
475
476 /*
477 * SATA interface between low level driver and command layer
478 */
sata_read(struct udevice * dev,lbaint_t blknr,lbaint_t blkcnt,void * buffer)479 static ulong sata_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
480 void *buffer)
481 {
482 struct sil_sata_priv *priv = dev_get_plat(dev);
483 int port_number = priv->port_num;
484 struct sil_sata *sata = priv->sil_sata_desc[port_number];
485 ulong rc;
486
487 if (sata->lba48)
488 rc = sil_sata_rw_lba48(sata, blknr, blkcnt, buffer, READ_CMD);
489 else
490 rc = sil_sata_rw_lba28(sata, blknr, blkcnt, buffer, READ_CMD);
491
492 return rc;
493 }
494
495 /*
496 * SATA interface between low level driver and command layer
497 */
sata_write(struct udevice * dev,lbaint_t blknr,lbaint_t blkcnt,const void * buffer)498 ulong sata_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
499 const void *buffer)
500 {
501 struct sil_sata_priv *priv = dev_get_plat(dev);
502 int port_number = priv->port_num;
503 struct sil_sata *sata = priv->sil_sata_desc[port_number];
504 ulong rc;
505
506 if (sata->lba48) {
507 rc = sil_sata_rw_lba48(sata, blknr, blkcnt, buffer, WRITE_CMD);
508 if (sata->wcache && sata->flush_ext)
509 sil_sata_cmd_flush_cache_ext(sata);
510 } else {
511 rc = sil_sata_rw_lba28(sata, blknr, blkcnt, buffer, WRITE_CMD);
512 if (sata->wcache && sata->flush)
513 sil_sata_cmd_flush_cache(sata);
514 }
515
516 return rc;
517 }
518
sil_init_sata(struct udevice * uc_dev,int dev)519 static int sil_init_sata(struct udevice *uc_dev, int dev)
520 {
521 struct sil_sata_priv *priv = dev_get_plat(uc_dev);
522 struct sil_sata *sata;
523 void *port;
524 u32 tmp;
525 int cnt;
526
527 printf("SATA#%d:\n", dev);
528
529 port = (void *)sata_info.iobase[1] +
530 PORT_REGS_SIZE * (dev - sata_info.portbase);
531
532 /* Initial PHY setting */
533 writel(0x20c, port + PORT_PHY_CFG);
534
535 /* clear port RST */
536 tmp = readl(port + PORT_CTRL_STAT);
537 if (tmp & PORT_CS_PORT_RST) {
538 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
539 tmp = ata_wait_register(port + PORT_CTRL_STAT,
540 PORT_CS_PORT_RST, PORT_CS_PORT_RST, 100);
541 if (tmp & PORT_CS_PORT_RST)
542 printf("Err: Failed to clear port RST\n");
543 }
544
545 /* Check if device is present */
546 for (cnt = 0; cnt < 100; cnt++) {
547 tmp = readl(port + PORT_SSTATUS);
548 if ((tmp & 0xF) == 0x3)
549 break;
550 mdelay(1);
551 }
552
553 tmp = readl(port + PORT_SSTATUS);
554 if ((tmp & 0xf) != 0x3) {
555 printf(" (No RDY)\n");
556 return 1;
557 }
558
559 /* Wait for port ready */
560 tmp = ata_wait_register(port + PORT_CTRL_STAT,
561 PORT_CS_RDY, PORT_CS_RDY, 100);
562 if ((tmp & PORT_CS_RDY) != PORT_CS_RDY) {
563 printf("%d port not ready.\n", dev);
564 return 1;
565 }
566
567 /* configure port */
568 sil_config_port(port);
569
570 /* Reset port */
571 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
572 readl(port + PORT_CTRL_STAT);
573 tmp = ata_wait_register(port + PORT_CTRL_STAT, PORT_CS_DEV_RST,
574 PORT_CS_DEV_RST, 100);
575 if (tmp & PORT_CS_DEV_RST) {
576 printf("%d port reset failed.\n", dev);
577 return 1;
578 }
579
580 sata = (struct sil_sata *)malloc(sizeof(struct sil_sata));
581 if (!sata) {
582 printf("%d no memory.\n", dev);
583 return 1;
584 }
585 memset((void *)sata, 0, sizeof(struct sil_sata));
586
587 /* Save the private struct to block device struct */
588 priv->sil_sata_desc[dev] = sata;
589 priv->port_num = dev;
590 sata->devno = uc_dev->parent;
591 sata->id = dev;
592 sata->port = port;
593 sprintf(sata->name, "SATA#%d", dev);
594 sil_cmd_soft_reset(sata);
595 tmp = readl(port + PORT_SSTATUS);
596 tmp = (tmp >> 4) & 0xf;
597 printf(" (%s)\n", sata_spd_string(tmp));
598
599 return 0;
600 }
601
scan_sata(struct udevice * blk_dev,int dev)602 static int scan_sata(struct udevice *blk_dev, int dev)
603 {
604 struct blk_desc *desc = dev_get_uclass_plat(blk_dev);
605 struct sil_sata_priv *priv = dev_get_plat(blk_dev);
606 struct sil_sata *sata = priv->sil_sata_desc[dev];
607 unsigned char serial[ATA_ID_SERNO_LEN + 1];
608 unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
609 unsigned char product[ATA_ID_PROD_LEN + 1];
610 u16 *id;
611
612 id = (u16 *)malloc(ATA_ID_WORDS * 2);
613 if (!id) {
614 printf("Id malloc failed\n");
615 return 1;
616 }
617 sil_cmd_identify_device(sata, id);
618
619 sil_sata_set_feature_by_id(sata, id);
620
621 /* Serial number */
622 ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
623
624 /* Firmware version */
625 ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
626
627 /* Product model */
628 ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
629
630 memcpy(desc->product, serial, sizeof(serial));
631 memcpy(desc->revision, firmware, sizeof(firmware));
632 memcpy(desc->vendor, product, sizeof(product));
633 desc->lba = ata_id_n_sectors(id);
634 #ifdef CONFIG_LBA48
635 desc->lba48 = sata->lba48;
636 #endif
637
638 #ifdef DEBUG
639 ata_dump_id(id);
640 #endif
641 free((void *)id);
642
643 return 0;
644 }
645
646 static const struct blk_ops sata_sil_blk_ops = {
647 .read = sata_read,
648 .write = sata_write,
649 };
650
651 U_BOOT_DRIVER(sata_sil_driver) = {
652 .name = "sata_sil_blk",
653 .id = UCLASS_BLK,
654 .ops = &sata_sil_blk_ops,
655 .plat_auto = sizeof(struct sil_sata_priv),
656 };
657
sil_unbind_device(struct udevice * dev)658 static int sil_unbind_device(struct udevice *dev)
659 {
660 int ret;
661
662 ret = device_remove(dev, DM_REMOVE_NORMAL);
663 if (ret)
664 return ret;
665
666 ret = device_unbind(dev);
667 if (ret)
668 return ret;
669
670 return 0;
671 }
672
sil_pci_probe(struct udevice * dev)673 static int sil_pci_probe(struct udevice *dev)
674 {
675 struct udevice *blk;
676 int failed_number;
677 char sata_name[10];
678 pci_dev_t devno;
679 u16 word;
680 int ret;
681 int i;
682
683 failed_number = 0;
684
685 /* Get PCI device number */
686 devno = dm_pci_get_bdf(dev);
687 if (devno == -1)
688 return 1;
689
690 dm_pci_read_config16(dev, PCI_DEVICE_ID, &word);
691
692 /* get the port count */
693 word &= 0xf;
694
695 sata_info.portbase = 0;
696 sata_info.maxport = sata_info.portbase + word;
697 sata_info.devno = devno;
698
699 /* Read out all BARs */
700 sata_info.iobase[0] = (ulong)dm_pci_map_bar(dev,
701 PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE,
702 PCI_REGION_MEM);
703 sata_info.iobase[1] = (ulong)dm_pci_map_bar(dev,
704 PCI_BASE_ADDRESS_2, 0, 0, PCI_REGION_TYPE,
705 PCI_REGION_MEM);
706
707 /* mask out the unused bits */
708 sata_info.iobase[0] &= 0xffffff80;
709 sata_info.iobase[1] &= 0xfffffc00;
710
711 /* Enable Bus Mastering and memory region */
712 dm_pci_write_config16(dev, PCI_COMMAND,
713 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
714
715 /* Check if mem accesses and Bus Mastering are enabled. */
716 dm_pci_read_config16(dev, PCI_COMMAND, &word);
717 if (!(word & PCI_COMMAND_MEMORY) ||
718 (!(word & PCI_COMMAND_MASTER))) {
719 printf("Error: Can not enable MEM access or Bus Mastering.\n");
720 debug("PCI command: %04x\n", word);
721 return 1;
722 }
723
724 /* GPIO off */
725 writel(0, (void *)(sata_info.iobase[0] + HOST_FLASH_CMD));
726 /* clear global reset & mask interrupts during initialization */
727 writel(0, (void *)(sata_info.iobase[0] + HOST_CTRL));
728
729 for (i = sata_info.portbase; i < sata_info.maxport; i++) {
730 snprintf(sata_name, sizeof(sata_name), "sil_sata%d", i);
731 ret = blk_create_devicef(dev, "sata_sil_blk", sata_name,
732 UCLASS_AHCI, -1, DEFAULT_BLKSZ,
733 0, &blk);
734 if (ret) {
735 debug("Can't create device\n");
736 return ret;
737 }
738
739 ret = sil_init_sata(blk, i);
740 if (ret) {
741 ret = sil_unbind_device(blk);
742 if (ret)
743 return ret;
744
745 failed_number++;
746 continue;
747 }
748
749 ret = scan_sata(blk, i);
750 if (ret) {
751 ret = sil_unbind_device(blk);
752 if (ret)
753 return ret;
754
755 failed_number++;
756 continue;
757 }
758
759 ret = device_probe(dev);
760 if (ret < 0) {
761 debug("Probing %s failed (%d)\n", dev->name, ret);
762 ret = sil_unbind_device(blk);
763 device_unbind(dev);
764 if (ret)
765 return ret;
766
767 failed_number++;
768 continue;
769 }
770 }
771
772 if (failed_number == sata_info.maxport)
773 return -ENODEV;
774 else
775 return 0;
776 }
777
sil_pci_remove(struct udevice * dev)778 static int sil_pci_remove(struct udevice *dev)
779 {
780 int i;
781 struct sil_sata *sata;
782 struct sil_sata_priv *priv;
783
784 priv = dev_get_priv(dev);
785
786 for (i = sata_info.portbase; i < sata_info.maxport; i++) {
787 sata = priv->sil_sata_desc[i];
788 if (sata)
789 free(sata);
790 }
791
792 return 0;
793 }
794
sata_sil_scan(struct udevice * dev)795 static int sata_sil_scan(struct udevice *dev)
796 {
797 /* Nothing to do here */
798
799 return 0;
800 }
801
802 struct sil_ops sata_sil_ops = {
803 .scan = sata_sil_scan,
804 };
805
806 static const struct udevice_id sil_pci_ids[] = {
807 { .compatible = "sil-pci-sample" },
808 { }
809 };
810
811 U_BOOT_DRIVER(sil_ahci_pci) = {
812 .name = "sil_ahci_pci",
813 .id = UCLASS_AHCI,
814 .of_match = sil_pci_ids,
815 .ops = &sata_sil_ops,
816 .probe = sil_pci_probe,
817 .remove = sil_pci_remove,
818 .priv_auto = sizeof(struct sil_sata_priv),
819 };
820
821 U_BOOT_PCI_DEVICE(sil_ahci_pci, supported);
822