1#
2# Cache controllers
3#
4
5menu "Cache Controller drivers"
6
7config CACHE
8	bool "Enable Driver Model for Cache controllers"
9	depends on DM
10	help
11	  Enable driver model for cache controllers that are found on
12	  most CPU's. Cache is memory that the CPU can access directly and
13	  is usually located on the same chip. This uclass can be used for
14	  configuring settings that be found from a device tree file.
15
16config L2X0_CACHE
17	tristate "PL310 cache driver"
18	select CACHE
19	depends on ARM
20	help
21	  This driver is for the PL310 cache controller commonly found on
22	  ARMv7(32-bit) devices. The driver configures the cache settings
23	  found in the device tree.
24
25config ANDES_L2_CACHE
26	bool "Andes L2 cache driver"
27	depends on RISCV
28	select CACHE
29	help
30	  Support Andes L2 cache controller in AE350 platform.
31	  It will configure tag and data ram timing control from the
32	  device tree and enable L2 cache.
33
34config NCORE_CACHE
35	bool "Arteris Ncore cache coherent unit driver"
36	select CACHE
37	help
38	  This driver is for the Arteris Ncore cache coherent unit (CCU)
39	  controller. The driver initializes cache directories and coherent
40	  agent interfaces.
41
42config SIFIVE_CCACHE
43	bool "SiFive composable cache"
44	select CACHE
45	help
46	  This driver is for SiFive Composable L2/L3 cache. It enables cache
47	  ways of composable cache.
48
49config SIFIVE_PL2
50	bool "SiFive private L2 cache"
51	select CACHE
52	help
53	  This driver is for SiFive Private L2 cache. It configures registers
54	  to enable the clock gating feature.
55
56endmenu
57