1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2019 Intel Corporation <www.intel.com>
4 */
5 #include <command.h>
6 #include <dm.h>
7
8 #include <asm/io.h>
9 #include <asm/pl310.h>
10
l2c310_of_parse_and_init(struct udevice * dev)11 static void l2c310_of_parse_and_init(struct udevice *dev)
12 {
13 u32 tag[3] = { 0, 0, 0 };
14 u32 saved_reg, prefetch;
15 struct pl310_regs *regs = dev_read_addr_ptr(dev);
16
17 /* Disable the L2 Cache */
18 clrbits_le32(®s->pl310_ctrl, L2X0_CTRL_EN);
19
20 saved_reg = readl(®s->pl310_aux_ctrl);
21 if (!dev_read_u32(dev, "prefetch-data", &prefetch)) {
22 if (prefetch)
23 saved_reg |= L310_AUX_CTRL_DATA_PREFETCH_MASK;
24 else
25 saved_reg &= ~L310_AUX_CTRL_DATA_PREFETCH_MASK;
26 }
27
28 if (!dev_read_u32(dev, "prefetch-instr", &prefetch)) {
29 if (prefetch)
30 saved_reg |= L310_AUX_CTRL_INST_PREFETCH_MASK;
31 else
32 saved_reg &= ~L310_AUX_CTRL_INST_PREFETCH_MASK;
33 }
34
35 if (dev_read_bool(dev, "arm,shared-override"))
36 saved_reg |= L310_SHARED_ATT_OVERRIDE_ENABLE;
37
38 writel(saved_reg, ®s->pl310_aux_ctrl);
39
40 saved_reg = readl(®s->pl310_tag_latency_ctrl);
41 if (!dev_read_u32_array(dev, "arm,tag-latency", tag, 3))
42 saved_reg |= L310_LATENCY_CTRL_RD(tag[0] - 1) |
43 L310_LATENCY_CTRL_WR(tag[1] - 1) |
44 L310_LATENCY_CTRL_SETUP(tag[2] - 1);
45 writel(saved_reg, ®s->pl310_tag_latency_ctrl);
46
47 saved_reg = readl(®s->pl310_data_latency_ctrl);
48 if (!dev_read_u32_array(dev, "arm,data-latency", tag, 3))
49 saved_reg |= L310_LATENCY_CTRL_RD(tag[0] - 1) |
50 L310_LATENCY_CTRL_WR(tag[1] - 1) |
51 L310_LATENCY_CTRL_SETUP(tag[2] - 1);
52 writel(saved_reg, ®s->pl310_data_latency_ctrl);
53
54 /* Enable the L2 cache */
55 setbits_le32(®s->pl310_ctrl, L2X0_CTRL_EN);
56 }
57
l2x0_probe(struct udevice * dev)58 static int l2x0_probe(struct udevice *dev)
59 {
60 l2c310_of_parse_and_init(dev);
61
62 return 0;
63 }
64
65 static const struct udevice_id l2x0_ids[] = {
66 { .compatible = "arm,pl310-cache" },
67 {}
68 };
69
70 U_BOOT_DRIVER(pl310_cache) = {
71 .name = "pl310_cache",
72 .id = UCLASS_CACHE,
73 .of_match = l2x0_ids,
74 .probe = l2x0_probe,
75 .flags = DM_FLAG_PRE_RELOC,
76 };
77