1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) 2023 SiFive
4  */
5 
6 #include <cache.h>
7 #include <dm.h>
8 #include <malloc.h>
9 #include <asm/io.h>
10 #include <dm/device.h>
11 #include <dm/device-internal.h>
12 
13 #define	SIFIVE_PL2CHICKENBIT_OFFSET			0x1000
14 #define	SIFIVE_PL2CHICKENBIT_REGIONCLOCKDISABLE_MASK	BIT(3)
15 
sifive_pl2_probe(struct udevice * dev)16 static int sifive_pl2_probe(struct udevice *dev)
17 {
18 	fdt_addr_t base;
19 	u32 val;
20 
21 	base = dev_read_addr(dev);
22 	if (base == FDT_ADDR_T_NONE)
23 		return -EINVAL;
24 
25 	/* Enable regionClockDisable bit */
26 	val = readl((void __iomem *)(base + SIFIVE_PL2CHICKENBIT_OFFSET));
27 	writel(val & ~SIFIVE_PL2CHICKENBIT_REGIONCLOCKDISABLE_MASK,
28 	       (void __iomem *)(base + SIFIVE_PL2CHICKENBIT_OFFSET));
29 
30 	return 0;
31 }
32 
33 static const struct udevice_id sifive_pl2_ids[] = {
34 	{ .compatible = "sifive,pl2cache0" },
35 	{ .compatible = "sifive,pl2cache1" },
36 	{}
37 };
38 
39 U_BOOT_DRIVER(sifive_pl2) = {
40 	.name = "sifive_pl2",
41 	.id = UCLASS_CACHE,
42 	.of_match = sifive_pl2_ids,
43 	.probe = sifive_pl2_probe,
44 };
45