1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * (C) Copyright 2016 Google, Inc
4 */
5
6 #include <clk-uclass.h>
7 #include <dm.h>
8 #include <log.h>
9 #include <asm/global_data.h>
10 #include <asm/io.h>
11 #include <asm/arch/scu_ast2500.h>
12 #include <dm/lists.h>
13 #include <dt-bindings/clock/aspeed-clock.h>
14 #include <dt-bindings/reset/ast2500-reset.h>
15 #include <linux/delay.h>
16 #include <linux/err.h>
17
18 /*
19 * MAC Clock Delay settings, taken from Aspeed SDK
20 */
21 #define RGMII_TXCLK_ODLY 8
22 #define RMII_RXCLK_IDLY 2
23
24 /*
25 * TGMII Clock Duty constants, taken from Aspeed SDK
26 */
27 #define RGMII2_TXCK_DUTY 0x66
28 #define RGMII1_TXCK_DUTY 0x64
29
30 #define D2PLL_DEFAULT_RATE (250 * 1000 * 1000)
31
32 /*
33 * AXI/AHB clock selection, taken from Aspeed SDK
34 */
35 #define SCU_HWSTRAP_AXIAHB_DIV_SHIFT 9
36 #define SCU_HWSTRAP_AXIAHB_DIV_MASK (0x7 << SCU_HWSTRAP_AXIAHB_DIV_SHIFT)
37
38 DECLARE_GLOBAL_DATA_PTR;
39
40 /*
41 * Clock divider/multiplier configuration struct.
42 * For H-PLL and M-PLL the formula is
43 * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1)
44 * M - Numerator
45 * N - Denumerator
46 * P - Post Divider
47 * They have the same layout in their control register.
48 *
49 * D-PLL and D2-PLL have extra divider (OD + 1), which is not
50 * yet needed and ignored by clock configurations.
51 */
52 struct ast2500_div_config {
53 unsigned int num;
54 unsigned int denum;
55 unsigned int post_div;
56 };
57
58 /*
59 * Get the rate of the M-PLL clock from input clock frequency and
60 * the value of the M-PLL Parameter Register.
61 */
ast2500_get_mpll_rate(ulong clkin,u32 mpll_reg)62 static ulong ast2500_get_mpll_rate(ulong clkin, u32 mpll_reg)
63 {
64 const ulong num = (mpll_reg & SCU_MPLL_NUM_MASK) >> SCU_MPLL_NUM_SHIFT;
65 const ulong denum = (mpll_reg & SCU_MPLL_DENUM_MASK)
66 >> SCU_MPLL_DENUM_SHIFT;
67 const ulong post_div = (mpll_reg & SCU_MPLL_POST_MASK)
68 >> SCU_MPLL_POST_SHIFT;
69
70 return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1);
71 }
72
73 /*
74 * Get the rate of the H-PLL clock from input clock frequency and
75 * the value of the H-PLL Parameter Register.
76 */
ast2500_get_hpll_rate(ulong clkin,u32 hpll_reg)77 static ulong ast2500_get_hpll_rate(ulong clkin, u32 hpll_reg)
78 {
79 const ulong num = (hpll_reg & SCU_HPLL_NUM_MASK) >> SCU_HPLL_NUM_SHIFT;
80 const ulong denum = (hpll_reg & SCU_HPLL_DENUM_MASK)
81 >> SCU_HPLL_DENUM_SHIFT;
82 const ulong post_div = (hpll_reg & SCU_HPLL_POST_MASK)
83 >> SCU_HPLL_POST_SHIFT;
84
85 return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1);
86 }
87
ast2500_get_clkin(struct ast2500_scu * scu)88 static ulong ast2500_get_clkin(struct ast2500_scu *scu)
89 {
90 return readl(&scu->hwstrap) & SCU_HWSTRAP_CLKIN_25MHZ
91 ? 25 * 1000 * 1000 : 24 * 1000 * 1000;
92 }
93
ast2500_get_hclk(ulong clkin,struct ast2500_scu * scu)94 static u32 ast2500_get_hclk(ulong clkin, struct ast2500_scu *scu)
95 {
96 u32 hpll_reg = readl(&scu->h_pll_param);
97 ulong axi_div = 2;
98 u32 rate;
99 ulong ahb_div = 1 + ((readl(&scu->hwstrap)
100 & SCU_HWSTRAP_AXIAHB_DIV_MASK)
101 >> SCU_HWSTRAP_AXIAHB_DIV_SHIFT);
102
103 rate = ast2500_get_hpll_rate(clkin, hpll_reg);
104
105 return (rate / axi_div / ahb_div);
106 }
107
108 /**
109 * Get current rate or uart clock
110 *
111 * @scu SCU registers
112 * @uart_index UART index, 1-5
113 *
114 * Return: current setting for uart clock rate
115 */
ast2500_get_uart_clk_rate(struct ast2500_scu * scu,int uart_index)116 static ulong ast2500_get_uart_clk_rate(struct ast2500_scu *scu, int uart_index)
117 {
118 /*
119 * ast2500 datasheet is very confusing when it comes to UART clocks,
120 * especially when CLKIN = 25 MHz. The settings are in
121 * different registers and it is unclear how they interact.
122 *
123 * This has only been tested with default settings and CLKIN = 24 MHz.
124 */
125 ulong uart_clkin;
126
127 if (readl(&scu->misc_ctrl2) &
128 (1 << (uart_index - 1 + SCU_MISC2_UARTCLK_SHIFT)))
129 uart_clkin = 192 * 1000 * 1000;
130 else
131 uart_clkin = 24 * 1000 * 1000;
132
133 if (readl(&scu->misc_ctrl1) & SCU_MISC_UARTCLK_DIV13)
134 uart_clkin /= 13;
135
136 return uart_clkin;
137 }
138
ast2500_clk_get_rate(struct clk * clk)139 static ulong ast2500_clk_get_rate(struct clk *clk)
140 {
141 struct ast2500_clk_priv *priv = dev_get_priv(clk->dev);
142 ulong clkin = ast2500_get_clkin(priv->scu);
143 ulong rate;
144
145 switch (clk->id) {
146 case ASPEED_CLK_HPLL:
147 /*
148 * This ignores dynamic/static slowdown of ARMCLK and may
149 * be inaccurate.
150 */
151 rate = ast2500_get_hpll_rate(clkin,
152 readl(&priv->scu->h_pll_param));
153 break;
154 case ASPEED_CLK_MPLL:
155 rate = ast2500_get_mpll_rate(clkin,
156 readl(&priv->scu->m_pll_param));
157 break;
158 case ASPEED_CLK_APB:
159 {
160 ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1)
161 & SCU_PCLK_DIV_MASK)
162 >> SCU_PCLK_DIV_SHIFT);
163 rate = ast2500_get_hpll_rate(clkin,
164 readl(&priv->
165 scu->h_pll_param));
166 rate = rate / apb_div;
167 }
168 break;
169 case ASPEED_CLK_AHB:
170 rate = ast2500_get_hclk(clkin, priv->scu);
171 break;
172 case ASPEED_CLK_SDIO:
173 {
174 ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1)
175 & SCU_SDCLK_DIV_MASK)
176 >> SCU_SDCLK_DIV_SHIFT);
177 rate = ast2500_get_hpll_rate(clkin,
178 readl(&priv->
179 scu->h_pll_param));
180 rate = rate / apb_div;
181 }
182 break;
183 case ASPEED_CLK_GATE_UART1CLK:
184 rate = ast2500_get_uart_clk_rate(priv->scu, 1);
185 break;
186 case ASPEED_CLK_GATE_UART2CLK:
187 rate = ast2500_get_uart_clk_rate(priv->scu, 2);
188 break;
189 case ASPEED_CLK_GATE_UART3CLK:
190 rate = ast2500_get_uart_clk_rate(priv->scu, 3);
191 break;
192 case ASPEED_CLK_GATE_UART4CLK:
193 rate = ast2500_get_uart_clk_rate(priv->scu, 4);
194 break;
195 case ASPEED_CLK_GATE_UART5CLK:
196 rate = ast2500_get_uart_clk_rate(priv->scu, 5);
197 break;
198 default:
199 debug("%s: unknown clk %ld\n", __func__, clk->id);
200 return -ENOENT;
201 }
202
203 return rate;
204 }
205
206 struct ast2500_clock_config {
207 ulong input_rate;
208 ulong rate;
209 struct ast2500_div_config cfg;
210 };
211
212 static const struct ast2500_clock_config ast2500_clock_config_defaults[] = {
213 { 24000000, 250000000, { .num = 124, .denum = 1, .post_div = 5 } },
214 };
215
ast2500_get_clock_config_default(ulong input_rate,ulong requested_rate,struct ast2500_div_config * cfg)216 static bool ast2500_get_clock_config_default(ulong input_rate,
217 ulong requested_rate,
218 struct ast2500_div_config *cfg)
219 {
220 int i;
221
222 for (i = 0; i < ARRAY_SIZE(ast2500_clock_config_defaults); i++) {
223 const struct ast2500_clock_config *default_cfg =
224 &ast2500_clock_config_defaults[i];
225 if (default_cfg->input_rate == input_rate &&
226 default_cfg->rate == requested_rate) {
227 *cfg = default_cfg->cfg;
228 return true;
229 }
230 }
231
232 return false;
233 }
234
235 /*
236 * @input_rate - the rate of input clock in Hz
237 * @requested_rate - desired output rate in Hz
238 * @div - this is an IN/OUT parameter, at input all fields of the config
239 * need to be set to their maximum allowed values.
240 * The result (the best config we could find), would also be returned
241 * in this structure.
242 *
243 * Return: The clock rate, when the resulting div_config is used.
244 */
ast2500_calc_clock_config(ulong input_rate,ulong requested_rate,struct ast2500_div_config * cfg)245 static ulong ast2500_calc_clock_config(ulong input_rate, ulong requested_rate,
246 struct ast2500_div_config *cfg)
247 {
248 /*
249 * The assumption is that kHz precision is good enough and
250 * also enough to avoid overflow when multiplying.
251 */
252 const ulong input_rate_khz = input_rate / 1000;
253 const ulong rate_khz = requested_rate / 1000;
254 const struct ast2500_div_config max_vals = *cfg;
255 struct ast2500_div_config it = { 0, 0, 0 };
256 ulong delta = rate_khz;
257 ulong new_rate_khz = 0;
258
259 /*
260 * Look for a well known frequency first.
261 */
262 if (ast2500_get_clock_config_default(input_rate, requested_rate, cfg))
263 return requested_rate;
264
265 for (; it.denum <= max_vals.denum; ++it.denum) {
266 for (it.post_div = 0; it.post_div <= max_vals.post_div;
267 ++it.post_div) {
268 it.num = (rate_khz * (it.post_div + 1) / input_rate_khz)
269 * (it.denum + 1);
270 if (it.num > max_vals.num)
271 continue;
272
273 new_rate_khz = (input_rate_khz
274 * ((it.num + 1) / (it.denum + 1)))
275 / (it.post_div + 1);
276
277 /* Keep the rate below requested one. */
278 if (new_rate_khz > rate_khz)
279 continue;
280
281 if (new_rate_khz - rate_khz < delta) {
282 delta = new_rate_khz - rate_khz;
283 *cfg = it;
284 if (delta == 0)
285 return new_rate_khz * 1000;
286 }
287 }
288 }
289
290 return new_rate_khz * 1000;
291 }
292
ast2500_configure_ddr(struct ast2500_scu * scu,ulong rate)293 static ulong ast2500_configure_ddr(struct ast2500_scu *scu, ulong rate)
294 {
295 ulong clkin = ast2500_get_clkin(scu);
296 u32 mpll_reg;
297 struct ast2500_div_config div_cfg = {
298 .num = (SCU_MPLL_NUM_MASK >> SCU_MPLL_NUM_SHIFT),
299 .denum = (SCU_MPLL_DENUM_MASK >> SCU_MPLL_DENUM_SHIFT),
300 .post_div = (SCU_MPLL_POST_MASK >> SCU_MPLL_POST_SHIFT),
301 };
302
303 ast2500_calc_clock_config(clkin, rate, &div_cfg);
304
305 mpll_reg = readl(&scu->m_pll_param);
306 mpll_reg &= ~(SCU_MPLL_POST_MASK | SCU_MPLL_NUM_MASK
307 | SCU_MPLL_DENUM_MASK);
308 mpll_reg |= (div_cfg.post_div << SCU_MPLL_POST_SHIFT)
309 | (div_cfg.num << SCU_MPLL_NUM_SHIFT)
310 | (div_cfg.denum << SCU_MPLL_DENUM_SHIFT);
311
312 ast_scu_unlock(scu);
313 writel(mpll_reg, &scu->m_pll_param);
314 ast_scu_lock(scu);
315
316 return ast2500_get_mpll_rate(clkin, mpll_reg);
317 }
318
ast2500_configure_mac(struct ast2500_scu * scu,int index)319 static ulong ast2500_configure_mac(struct ast2500_scu *scu, int index)
320 {
321 ulong clkin = ast2500_get_clkin(scu);
322 ulong hpll_rate = ast2500_get_hpll_rate(clkin,
323 readl(&scu->h_pll_param));
324 ulong required_rate;
325 u32 hwstrap;
326 u32 divisor;
327 u32 reset_bit;
328 u32 clkstop_bit;
329
330 /*
331 * According to data sheet, for 10/100 mode the MAC clock frequency
332 * should be at least 25MHz and for 1000 mode at least 100MHz
333 */
334 hwstrap = readl(&scu->hwstrap);
335 if (hwstrap & (SCU_HWSTRAP_MAC1_RGMII | SCU_HWSTRAP_MAC2_RGMII))
336 required_rate = 100 * 1000 * 1000;
337 else
338 required_rate = 25 * 1000 * 1000;
339
340 divisor = hpll_rate / required_rate;
341
342 if (divisor < 4) {
343 /* Clock can't run fast enough, but let's try anyway */
344 debug("MAC clock too slow\n");
345 divisor = 4;
346 } else if (divisor > 16) {
347 /* Can't slow down the clock enough, but let's try anyway */
348 debug("MAC clock too fast\n");
349 divisor = 16;
350 }
351
352 switch (index) {
353 case 1:
354 reset_bit = SCU_SYSRESET_MAC1;
355 clkstop_bit = SCU_CLKSTOP_MAC1;
356 break;
357 case 2:
358 reset_bit = SCU_SYSRESET_MAC2;
359 clkstop_bit = SCU_CLKSTOP_MAC2;
360 break;
361 default:
362 return -EINVAL;
363 }
364
365 ast_scu_unlock(scu);
366 clrsetbits_le32(&scu->clk_sel1, SCU_MACCLK_MASK,
367 ((divisor - 2) / 2) << SCU_MACCLK_SHIFT);
368
369 /*
370 * Disable MAC, start its clock and re-enable it.
371 * The procedure and the delays (100us & 10ms) are
372 * specified in the datasheet.
373 */
374 setbits_le32(&scu->sysreset_ctrl1, reset_bit);
375 udelay(100);
376 clrbits_le32(&scu->clk_stop_ctrl1, clkstop_bit);
377 mdelay(10);
378 clrbits_le32(&scu->sysreset_ctrl1, reset_bit);
379
380 writel((RGMII2_TXCK_DUTY << SCU_CLKDUTY_RGMII2TXCK_SHIFT)
381 | (RGMII1_TXCK_DUTY << SCU_CLKDUTY_RGMII1TXCK_SHIFT),
382 &scu->clk_duty_sel);
383
384 ast_scu_lock(scu);
385
386 return required_rate;
387 }
388
ast2500_configure_d2pll(struct ast2500_scu * scu,ulong rate)389 static ulong ast2500_configure_d2pll(struct ast2500_scu *scu, ulong rate)
390 {
391 /*
392 * The values and the meaning of the next three
393 * parameters are undocumented. Taken from Aspeed SDK.
394 *
395 * TODO(clg@kaod.org): the SIP and SIC values depend on the
396 * Numerator value
397 */
398 const u32 d2_pll_ext_param = 0x2c;
399 const u32 d2_pll_sip = 0x11;
400 const u32 d2_pll_sic = 0x18;
401 u32 clk_delay_settings =
402 (RMII_RXCLK_IDLY << SCU_MICDS_MAC1RMII_RDLY_SHIFT)
403 | (RMII_RXCLK_IDLY << SCU_MICDS_MAC2RMII_RDLY_SHIFT)
404 | (RGMII_TXCLK_ODLY << SCU_MICDS_MAC1RGMII_TXDLY_SHIFT)
405 | (RGMII_TXCLK_ODLY << SCU_MICDS_MAC2RGMII_TXDLY_SHIFT);
406 struct ast2500_div_config div_cfg = {
407 .num = SCU_D2PLL_NUM_MASK >> SCU_D2PLL_NUM_SHIFT,
408 .denum = SCU_D2PLL_DENUM_MASK >> SCU_D2PLL_DENUM_SHIFT,
409 .post_div = SCU_D2PLL_POST_MASK >> SCU_D2PLL_POST_SHIFT,
410 };
411 ulong clkin = ast2500_get_clkin(scu);
412 ulong new_rate;
413
414 ast_scu_unlock(scu);
415 writel((d2_pll_ext_param << SCU_D2PLL_EXT1_PARAM_SHIFT)
416 | SCU_D2PLL_EXT1_OFF
417 | SCU_D2PLL_EXT1_RESET, &scu->d2_pll_ext_param[0]);
418
419 /*
420 * Select USB2.0 port1 PHY clock as a clock source for GCRT.
421 * This would disconnect it from D2-PLL.
422 */
423 clrsetbits_le32(&scu->misc_ctrl1, SCU_MISC_D2PLL_OFF,
424 SCU_MISC_GCRT_USB20CLK);
425
426 new_rate = ast2500_calc_clock_config(clkin, rate, &div_cfg);
427 writel((d2_pll_sip << SCU_D2PLL_SIP_SHIFT)
428 | (d2_pll_sic << SCU_D2PLL_SIC_SHIFT)
429 | (div_cfg.num << SCU_D2PLL_NUM_SHIFT)
430 | (div_cfg.denum << SCU_D2PLL_DENUM_SHIFT)
431 | (div_cfg.post_div << SCU_D2PLL_POST_SHIFT),
432 &scu->d2_pll_param);
433
434 clrbits_le32(&scu->d2_pll_ext_param[0],
435 SCU_D2PLL_EXT1_OFF | SCU_D2PLL_EXT1_RESET);
436
437 clrsetbits_le32(&scu->misc_ctrl2,
438 SCU_MISC2_RGMII_HPLL | SCU_MISC2_RMII_MPLL
439 | SCU_MISC2_RGMII_CLKDIV_MASK |
440 SCU_MISC2_RMII_CLKDIV_MASK,
441 (4 << SCU_MISC2_RMII_CLKDIV_SHIFT));
442
443 writel(clk_delay_settings | SCU_MICDS_RGMIIPLL, &scu->mac_clk_delay);
444 writel(clk_delay_settings, &scu->mac_clk_delay_100M);
445 writel(clk_delay_settings, &scu->mac_clk_delay_10M);
446
447 ast_scu_lock(scu);
448
449 return new_rate;
450 }
451
452 #define SCU_CLKSTOP_SDIO 27
ast2500_enable_sdclk(struct ast2500_scu * scu)453 static ulong ast2500_enable_sdclk(struct ast2500_scu *scu)
454 {
455 u32 reset_bit;
456 u32 clkstop_bit;
457
458 reset_bit = BIT(ASPEED_RESET_SDIO);
459 clkstop_bit = BIT(SCU_CLKSTOP_SDIO);
460
461 setbits_le32(&scu->sysreset_ctrl1, reset_bit);
462 udelay(100);
463 //enable clk
464 clrbits_le32(&scu->clk_stop_ctrl1, clkstop_bit);
465 mdelay(10);
466 clrbits_le32(&scu->sysreset_ctrl1, reset_bit);
467
468 return 0;
469 }
470
ast2500_clk_set_rate(struct clk * clk,ulong rate)471 static ulong ast2500_clk_set_rate(struct clk *clk, ulong rate)
472 {
473 struct ast2500_clk_priv *priv = dev_get_priv(clk->dev);
474
475 ulong new_rate;
476 switch (clk->id) {
477 case ASPEED_CLK_MPLL:
478 new_rate = ast2500_configure_ddr(priv->scu, rate);
479 break;
480 case ASPEED_CLK_D2PLL:
481 new_rate = ast2500_configure_d2pll(priv->scu, rate);
482 break;
483 default:
484 debug("%s: unknown clk %ld\n", __func__, clk->id);
485 return -ENOENT;
486 }
487
488 return new_rate;
489 }
490
ast2500_clk_enable(struct clk * clk)491 static int ast2500_clk_enable(struct clk *clk)
492 {
493 struct ast2500_clk_priv *priv = dev_get_priv(clk->dev);
494
495 switch (clk->id) {
496 case ASPEED_CLK_SDIO:
497 if (readl(&priv->scu->clk_stop_ctrl1) & SCU_CLKSTOP_SDCLK) {
498 ast_scu_unlock(priv->scu);
499
500 setbits_le32(&priv->scu->sysreset_ctrl1,
501 SCU_SYSRESET_SDIO);
502 udelay(100);
503 clrbits_le32(&priv->scu->clk_stop_ctrl1,
504 SCU_CLKSTOP_SDCLK);
505 mdelay(10);
506 clrbits_le32(&priv->scu->sysreset_ctrl1,
507 SCU_SYSRESET_SDIO);
508
509 ast_scu_lock(priv->scu);
510 }
511 break;
512 /*
513 * For MAC clocks the clock rate is
514 * configured based on whether RGMII or RMII mode has been selected
515 * through hardware strapping.
516 */
517 case ASPEED_CLK_GATE_MAC1CLK:
518 ast2500_configure_mac(priv->scu, 1);
519 break;
520 case ASPEED_CLK_GATE_MAC2CLK:
521 ast2500_configure_mac(priv->scu, 2);
522 break;
523 case ASPEED_CLK_D2PLL:
524 ast2500_configure_d2pll(priv->scu, D2PLL_DEFAULT_RATE);
525 break;
526 case ASPEED_CLK_GATE_SDCLK:
527 ast2500_enable_sdclk(priv->scu);
528 break;
529 default:
530 debug("%s: unknown clk %ld\n", __func__, clk->id);
531 return -ENOENT;
532 }
533
534 return 0;
535 }
536
537 struct clk_ops ast2500_clk_ops = {
538 .get_rate = ast2500_clk_get_rate,
539 .set_rate = ast2500_clk_set_rate,
540 .enable = ast2500_clk_enable,
541 };
542
ast2500_clk_of_to_plat(struct udevice * dev)543 static int ast2500_clk_of_to_plat(struct udevice *dev)
544 {
545 struct ast2500_clk_priv *priv = dev_get_priv(dev);
546
547 priv->scu = devfdt_get_addr_ptr(dev);
548 if (IS_ERR(priv->scu))
549 return PTR_ERR(priv->scu);
550
551 return 0;
552 }
553
ast2500_clk_bind(struct udevice * dev)554 static int ast2500_clk_bind(struct udevice *dev)
555 {
556 int ret;
557
558 /* The reset driver does not have a device node, so bind it here */
559 ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev);
560 if (ret)
561 debug("Warning: No reset driver: ret=%d\n", ret);
562
563 return 0;
564 }
565
566 static const struct udevice_id ast2500_clk_ids[] = {
567 { .compatible = "aspeed,ast2500-scu" },
568 { }
569 };
570
571 U_BOOT_DRIVER(aspeed_ast2500_scu) = {
572 .name = "aspeed_ast2500_scu",
573 .id = UCLASS_CLK,
574 .of_match = ast2500_clk_ids,
575 .priv_auto = sizeof(struct ast2500_clk_priv),
576 .ops = &ast2500_clk_ops,
577 .bind = ast2500_clk_bind,
578 .of_to_plat = ast2500_clk_of_to_plat,
579 };
580