1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
5 * Copyright 2019 NXP
6 *
7 * Gated clock implementation
8 */
9
10 #define LOG_CATEGORY UCLASS_CLK
11
12 #include <clk.h>
13 #include <log.h>
14 #include <clk-uclass.h>
15 #include <malloc.h>
16 #include <asm/io.h>
17 #include <dm/device.h>
18 #include <dm/device_compat.h>
19 #include <dm/devres.h>
20 #include <linux/bitops.h>
21 #include <linux/clk-provider.h>
22 #include <linux/err.h>
23 #include <linux/printk.h>
24
25 #include "clk.h"
26
27 #define UBOOT_DM_CLK_GATE "clk_gate"
28
29 /**
30 * DOC: basic gatable clock which can gate and ungate it's output
31 *
32 * Traits of this clock:
33 * prepare - clk_(un)prepare only ensures parent is (un)prepared
34 * enable - clk_enable and clk_disable are functional & control gating
35 * rate - inherits rate from parent. No clk_set_rate support
36 * parent - fixed parent. No clk_set_parent support
37 */
38
39 /*
40 * It works on following logic:
41 *
42 * For enabling clock, enable = 1
43 * set2dis = 1 -> clear bit -> set = 0
44 * set2dis = 0 -> set bit -> set = 1
45 *
46 * For disabling clock, enable = 0
47 * set2dis = 1 -> set bit -> set = 1
48 * set2dis = 0 -> clear bit -> set = 0
49 *
50 * So, result is always: enable xor set2dis.
51 */
clk_gate_endisable(struct clk * clk,int enable)52 static void clk_gate_endisable(struct clk *clk, int enable)
53 {
54 struct clk_gate *gate = to_clk_gate(clk);
55 int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
56 u32 reg;
57
58 set ^= enable;
59
60 if (gate->flags & CLK_GATE_HIWORD_MASK) {
61 reg = BIT(gate->bit_idx + 16);
62 if (set)
63 reg |= BIT(gate->bit_idx);
64 } else {
65 #if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF)
66 reg = gate->io_gate_val;
67 #else
68 reg = readl(gate->reg);
69 #endif
70
71 if (set)
72 reg |= BIT(gate->bit_idx);
73 else
74 reg &= ~BIT(gate->bit_idx);
75 }
76
77 writel(reg, gate->reg);
78 }
79
clk_gate_enable(struct clk * clk)80 static int clk_gate_enable(struct clk *clk)
81 {
82 clk_gate_endisable(clk, 1);
83
84 return 0;
85 }
86
clk_gate_disable(struct clk * clk)87 static int clk_gate_disable(struct clk *clk)
88 {
89 clk_gate_endisable(clk, 0);
90
91 return 0;
92 }
93
clk_gate_is_enabled(struct clk * clk)94 int clk_gate_is_enabled(struct clk *clk)
95 {
96 struct clk_gate *gate = to_clk_gate(clk);
97 u32 reg;
98
99 #if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF)
100 reg = gate->io_gate_val;
101 #else
102 reg = readl(gate->reg);
103 #endif
104
105 /* if a set bit disables this clk, flip it before masking */
106 if (gate->flags & CLK_GATE_SET_TO_DISABLE)
107 reg ^= BIT(gate->bit_idx);
108
109 reg &= BIT(gate->bit_idx);
110
111 return reg ? 1 : 0;
112 }
113
114 const struct clk_ops clk_gate_ops = {
115 .enable = clk_gate_enable,
116 .disable = clk_gate_disable,
117 .get_rate = clk_generic_get_rate,
118 };
119
clk_register_gate(struct udevice * dev,const char * name,const char * parent_name,unsigned long flags,void __iomem * reg,u8 bit_idx,u8 clk_gate_flags,spinlock_t * lock)120 struct clk *clk_register_gate(struct udevice *dev, const char *name,
121 const char *parent_name, unsigned long flags,
122 void __iomem *reg, u8 bit_idx,
123 u8 clk_gate_flags, spinlock_t *lock)
124 {
125 struct clk_gate *gate;
126 struct clk *clk;
127 int ret;
128
129 if (clk_gate_flags & CLK_GATE_HIWORD_MASK) {
130 if (bit_idx > 15) {
131 dev_err(dev, "gate bit exceeds LOWORD field\n");
132 return ERR_PTR(-EINVAL);
133 }
134 }
135
136 /* allocate the gate */
137 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
138 if (!gate)
139 return ERR_PTR(-ENOMEM);
140
141 /* struct clk_gate assignments */
142 gate->reg = reg;
143 gate->bit_idx = bit_idx;
144 gate->flags = clk_gate_flags;
145 #if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF)
146 gate->io_gate_val = *(u32 *)reg;
147 #endif
148
149 clk = &gate->clk;
150 clk->flags = flags;
151
152 ret = clk_register(clk, UBOOT_DM_CLK_GATE, name,
153 clk_resolve_parent_clk(dev, parent_name));
154 if (ret) {
155 kfree(gate);
156 return ERR_PTR(ret);
157 }
158
159 return clk;
160 }
161
162 U_BOOT_DRIVER(clk_gate) = {
163 .name = UBOOT_DM_CLK_GATE,
164 .id = UCLASS_CLK,
165 .ops = &clk_gate_ops,
166 .flags = DM_FLAG_PRE_RELOC,
167 };
168