1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2020 Microchip Technology Inc.
4 * Padmarao Begari <padmarao.begari@microchip.com>
5 */
6 #include <clk.h>
7 #include <clk-uclass.h>
8 #include <dm.h>
9 #include <log.h>
10 #include <dm/device.h>
11 #include <dm/devres.h>
12 #include <dm/ofnode.h>
13 #include <dm/uclass.h>
14 #include <regmap.h>
15 #include <syscon.h>
16 #include <dt-bindings/clock/microchip-mpfs-clock.h>
17 #include <linux/err.h>
18
19 #include "mpfs_clk.h"
20
mpfs_clk_syscon_probe(struct udevice * dev,void __iomem ** msspll_base,struct regmap ** regmap)21 static int mpfs_clk_syscon_probe(struct udevice *dev, void __iomem **msspll_base,
22 struct regmap **regmap)
23 {
24 ofnode node;
25
26 node = ofnode_by_compatible(ofnode_null(), "microchip,mpfs-mss-top-sysreg");
27 if (!ofnode_valid(node))
28 return -ENODEV;
29
30 *regmap = syscon_node_to_regmap(node);
31 if (IS_ERR(regmap))
32 return PTR_ERR(regmap);
33
34 *msspll_base = dev_read_addr_index_ptr(dev, 0);
35
36 return 0;
37 }
38
mpfs_clk_old_format_probe(struct udevice * dev,void __iomem ** msspll_base,struct regmap ** regmap)39 static int mpfs_clk_old_format_probe(struct udevice *dev, void __iomem **msspll_base,
40 struct regmap **regmap)
41 {
42 int ret;
43
44 ret = regmap_init_mem_index(dev_ofnode(dev), regmap, 0);
45 if (ret)
46 return ret;
47
48 /*
49 * The original devicetrees for mpfs messed up & defined the msspll's
50 * output as a fixed-frequency, 600 MHz clock & used that as the input
51 * for the clock controller node. The msspll is however not a fixed
52 * frequency clock and later devicetrees handled this properly. Check
53 * the devicetree & if it is one of the fixed ones, register the msspll.
54 * Otherwise, skip registering it & pass the reference clock directly
55 * to the cfg clock registration function.
56 */
57 *msspll_base = dev_read_addr_index_ptr(dev, 1);
58
59 return 0;
60 }
61
mpfs_clk_probe(struct udevice * dev)62 static int mpfs_clk_probe(struct udevice *dev)
63 {
64 struct clk *parent_clk = dev_get_priv(dev);
65 struct clk clk_msspll = { .id = CLK_MSSPLL };
66 struct regmap *regmap;
67 void __iomem *msspll_base;
68 int ret;
69
70 ret = clk_get_by_index(dev, 0, parent_clk);
71 if (ret)
72 return ret;
73
74 ret = mpfs_clk_syscon_probe(dev, &msspll_base, ®map);
75 if (ret) {
76 ret = mpfs_clk_old_format_probe(dev, &msspll_base, ®map);
77 if (ret)
78 return ret;
79 }
80
81 if (msspll_base) {
82 ret = mpfs_clk_register_msspll(msspll_base, parent_clk);
83 if (ret)
84 return ret;
85
86 clk_request(dev, &clk_msspll);
87 parent_clk = &clk_msspll;
88 }
89
90 ret = mpfs_clk_register_cfgs(parent_clk, regmap);
91 if (ret)
92 return ret;
93
94 ret = mpfs_clk_register_periphs(dev, regmap);
95
96 return ret;
97 }
98
99 static const struct udevice_id mpfs_of_match[] = {
100 { .compatible = "microchip,mpfs-clkcfg" },
101 { }
102 };
103
104 U_BOOT_DRIVER(mpfs_clk) = {
105 .name = "mpfs_clk",
106 .id = UCLASS_CLK,
107 .of_match = mpfs_of_match,
108 .ops = &ccf_clk_ops,
109 .probe = mpfs_clk_probe,
110 .priv_auto = sizeof(struct clk),
111 .flags = DM_FLAG_PRE_RELOC,
112 };
113