1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2020 Microchip Technology Inc. 4 * Padmarao Begari <padmarao.begari@microchip.com> 5 */ 6 #ifndef __MICROCHIP_MPFS_CLK_H 7 #define __MICROCHIP_MPFS_CLK_H 8 9 #include <linux/clk-provider.h> 10 #include <regmap.h> 11 /** 12 * mpfs_clk_register_cfgs() - register configuration clocks 13 * 14 * @base: base address of the mpfs system register. 15 * @parent: a pointer to parent clock. 16 * Return: zero on success, or a negative error code. 17 */ 18 int mpfs_clk_register_cfgs(struct clk *parent, struct regmap *regmap); 19 /** 20 * mpfs_clk_register_msspll() - register the mss pll 21 * 22 * @base: base address of the mpfs system register. 23 * @parent: a pointer to parent clock. 24 * Return: zero on success, or a negative error code. 25 */ 26 int mpfs_clk_register_msspll(void __iomem *base, struct clk *parent); 27 /** 28 * mpfs_clk_register_periphs() - register peripheral clocks 29 * 30 * @base: base address of the mpfs system register. 31 * @dev: udevice representing the clock controller. 32 * Return: zero on success, or a negative error code. 33 */ 34 int mpfs_clk_register_periphs(struct udevice *dev, struct regmap *regmap); 35 /** 36 * divider_get_val() - get the clock divider value 37 * 38 * @rate: requested clock rate. 39 * @parent_rate: parent clock rate. 40 * @table: a pointer to clock divider table. 41 * @width: width of the divider bit field. 42 * @flags: common clock framework flags. 43 * Return: divider value on success, or a negative error code. 44 */ 45 int divider_get_val(unsigned long rate, unsigned long parent_rate, 46 const struct clk_div_table *table, 47 u8 width, unsigned long flags); 48 49 #endif /* __MICROCHIP_MPFS_CLK_H */ 50