1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2022 Microchip Technology Inc.
4 */
5 #include <clk.h>
6 #include <clk-uclass.h>
7 #include <asm/io.h>
8 #include <dm/device.h>
9 #include <dm/devres.h>
10 #include <dm/uclass.h>
11 #include <dt-bindings/clock/microchip-mpfs-clock.h>
12 #include <linux/err.h>
13
14 #include "mpfs_clk.h"
15
16 #define MPFS_MSSPLL_CLOCK "mpfs_msspll_clock"
17
18 /* address offset of control registers */
19 #define REG_MSSPLL_REF_CR 0x08u
20 #define REG_MSSPLL_POSTDIV_CR 0x10u
21 #define REG_MSSPLL_SSCG_2_CR 0x2Cu
22
23 #define MSSPLL_FBDIV_SHIFT 0x00u
24 #define MSSPLL_FBDIV_WIDTH 0x0Cu
25 #define MSSPLL_REFDIV_SHIFT 0x08u
26 #define MSSPLL_REFDIV_WIDTH 0x06u
27 #define MSSPLL_POSTDIV_SHIFT 0x08u
28 #define MSSPLL_POSTDIV_WIDTH 0x07u
29 #define MSSPLL_FIXED_DIV 4u
30
31 /**
32 * struct mpfs_msspll_hw_clock
33 * @id: index of the msspll clock
34 * @name: the msspll clocks name
35 * @reg_offset: offset to the core complex's output of the msspll
36 * @shift: shift to the divider bit field of a msspll clock output
37 * @width: width of the divider bit field of the msspll clock output
38 * @flags: common clock framework flags
39 * @prate: the reference clock rate
40 * @hw: clock instance
41 */
42 struct mpfs_msspll_hw_clock {
43 void __iomem *base;
44 unsigned int id;
45 const char *name;
46 u32 reg_offset;
47 u32 shift;
48 u32 width;
49 u32 flags;
50 u32 prate;
51 struct clk hw;
52 };
53
54 #define to_mpfs_msspll_clk(_hw) container_of(_hw, struct mpfs_msspll_hw_clock, hw)
55
mpfs_clk_msspll_recalc_rate(struct clk * hw)56 static unsigned long mpfs_clk_msspll_recalc_rate(struct clk *hw)
57 {
58 struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw);
59 void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset;
60 void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR;
61 void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR;
62 u32 mult, ref_div, postdiv;
63 unsigned long temp;
64
65 mult = readl(mult_addr) >> MSSPLL_FBDIV_SHIFT;
66 mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH);
67 ref_div = readl(ref_div_addr) >> MSSPLL_REFDIV_SHIFT;
68 ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH);
69 postdiv = readl(postdiv_addr) >> MSSPLL_POSTDIV_SHIFT;
70 postdiv &= clk_div_mask(MSSPLL_POSTDIV_WIDTH);
71
72 temp = msspll_hw->prate / (ref_div * MSSPLL_FIXED_DIV * postdiv);
73 return temp * mult;
74 }
75
76 #define CLK_PLL(_id, _name, _shift, _width, _reg_offset, _flags) { \
77 .id = _id, \
78 .name = _name, \
79 .shift = _shift, \
80 .width = _width, \
81 .reg_offset = _reg_offset, \
82 .flags = _flags, \
83 }
84
85 static struct mpfs_msspll_hw_clock mpfs_msspll_clks[] = {
86 CLK_PLL(CLK_MSSPLL, "clk_msspll", MSSPLL_FBDIV_SHIFT,
87 MSSPLL_FBDIV_WIDTH, REG_MSSPLL_SSCG_2_CR, 0),
88 };
89
mpfs_clk_register_msspll(void __iomem * base,struct clk * parent)90 int mpfs_clk_register_msspll(void __iomem *base, struct clk *parent)
91 {
92 int id, ret;
93 const char *name;
94 struct clk *hw;
95
96 hw = &mpfs_msspll_clks[0].hw;
97 mpfs_msspll_clks[0].base = base;
98 mpfs_msspll_clks[0].prate = clk_get_rate(parent);
99 name = mpfs_msspll_clks[0].name;
100 ret = clk_register(hw, MPFS_MSSPLL_CLOCK, name, parent->dev->name);
101 if (ret)
102 ERR_PTR(ret);
103 id = mpfs_msspll_clks[0].id;
104 clk_dm(id, hw);
105
106 return 0;
107 }
108
109 const struct clk_ops mpfs_msspll_clk_ops = {
110 .get_rate = mpfs_clk_msspll_recalc_rate,
111 };
112
113 U_BOOT_DRIVER(mpfs_msspll_clock) = {
114 .name = MPFS_MSSPLL_CLOCK,
115 .id = UCLASS_CLK,
116 .ops = &mpfs_msspll_clk_ops,
117 };
118
119