1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2020 Microchip Technology Inc.
4 * Padmarao Begari <padmarao.begari@microchip.com>
5 */
6 #include <clk.h>
7 #include <clk-uclass.h>
8 #include <asm/io.h>
9 #include <dm/device.h>
10 #include <dm/devres.h>
11 #include <dm/uclass.h>
12 #include <regmap.h>
13 #include <dt-bindings/clock/microchip-mpfs-clock.h>
14 #include <linux/err.h>
15
16 #include "mpfs_clk.h"
17
18 #define MPFS_PERIPH_CLOCK "mpfs_periph_clock"
19
20 #define REG_CLOCK_CONFIG_CR 0x08
21 #define REG_SUBBLK_CLOCK_CR 0x84
22 #define REG_SUBBLK_RESET_CR 0x88
23
24 #define CFG_CPU_SHIFT 0x0
25 #define CFG_AXI_SHIFT 0x2
26 #define CFG_AHB_SHIFT 0x4
27 #define CFG_WIDTH 0x2
28
29 /**
30 * struct mpfs_periph_clock - per instance of peripheral clock
31 * @id: index of a peripheral clock
32 * @parent_id: index of the parent clock
33 * @name: name of a peripheral clock
34 * @shift: shift to a peripheral clock bit field
35 * @flags: common clock framework flags
36 */
37 struct mpfs_periph_clock {
38 unsigned int id;
39 unsigned int parent_id;
40 const char *name;
41 u8 shift;
42 unsigned long flags;
43 };
44
45 /**
46 * struct mpfs_periph_hw_clock - hardware peripheral clock
47 * @periph: peripheral clock instance
48 * @sys_base: base address of the mpfs system register
49 * @prate: the pll clock rate
50 * @hw: clock instance
51 */
52 struct mpfs_periph_hw_clock {
53 struct mpfs_periph_clock periph;
54 struct regmap *regmap;
55 u32 prate;
56 struct clk hw;
57 };
58
59 #define to_mpfs_periph_clk(_hw) container_of(_hw, struct mpfs_periph_hw_clock, hw)
60
mpfs_periph_clk_enable(struct clk * hw)61 static int mpfs_periph_clk_enable(struct clk *hw)
62 {
63 struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);
64 struct mpfs_periph_clock *periph = &periph_hw->periph;
65 u32 reg;
66
67 if (periph->flags != CLK_IS_CRITICAL) {
68 regmap_read(periph_hw->regmap, REG_SUBBLK_RESET_CR, ®);
69 reg &= ~(1u << periph->shift);
70 regmap_write(periph_hw->regmap, REG_SUBBLK_RESET_CR, reg);
71
72 regmap_read(periph_hw->regmap, REG_SUBBLK_CLOCK_CR, ®);
73 reg |= (1u << periph->shift);
74 regmap_write(periph_hw->regmap, REG_SUBBLK_CLOCK_CR, reg);
75 }
76
77 return 0;
78 }
79
mpfs_periph_clk_disable(struct clk * hw)80 static int mpfs_periph_clk_disable(struct clk *hw)
81 {
82 struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);
83 struct mpfs_periph_clock *periph = &periph_hw->periph;
84 u32 reg;
85
86 if (periph->flags != CLK_IS_CRITICAL) {
87 regmap_read(periph_hw->regmap, REG_SUBBLK_RESET_CR, ®);
88 reg |= (1u << periph->shift);
89 regmap_write(periph_hw->regmap, REG_SUBBLK_RESET_CR, reg);
90
91 regmap_read(periph_hw->regmap, REG_SUBBLK_CLOCK_CR, ®);
92 reg &= ~(1u << periph->shift);
93 regmap_write(periph_hw->regmap, REG_SUBBLK_CLOCK_CR, reg);
94 }
95
96 return 0;
97 }
98
mpfs_periph_clk_recalc_rate(struct clk * hw)99 static ulong mpfs_periph_clk_recalc_rate(struct clk *hw)
100 {
101 struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);
102
103 return periph_hw->prate;
104
105 }
106
107 #define CLK_PERIPH(_id, _name, _parent_id, _shift, _flags) { \
108 .periph.id = _id, \
109 .periph.parent_id = _parent_id, \
110 .periph.name = _name, \
111 .periph.shift = _shift, \
112 .periph.flags = _flags, \
113 }
114
115 /*
116 * Critical clocks:
117 * - CLK_ENVM: reserved by hart software services (hss) superloop monitor/m mode interrupt
118 * trap handler
119 * - CLK_MMUART0: reserved by the hss
120 * - CLK_DDRC: provides clock to the ddr subsystem
121 * - CLK_RTC: the onboard RTC's AHB bus clock must be kept running as the rtc will stop
122 * if the AHB interface clock is disabled
123 * - CLK_FICx: these provide the processor side clocks to the "FIC" (Fabric InterConnect)
124 * clock domain crossers which provide the interface to the FPGA fabric. Disabling them
125 * causes the FPGA fabric to go into reset.
126 * - CLK_ATHENA: The athena clock is FIC4, which is reserved for the Athena TeraFire.
127 */
128
129 static struct mpfs_periph_hw_clock mpfs_periph_clks[] = {
130 CLK_PERIPH(CLK_ENVM, "clk_periph_envm", CLK_AHB, 0, CLK_IS_CRITICAL),
131 CLK_PERIPH(CLK_MAC0, "clk_periph_mac0", CLK_AHB, 1, 0),
132 CLK_PERIPH(CLK_MAC1, "clk_periph_mac1", CLK_AHB, 2, 0),
133 CLK_PERIPH(CLK_MMC, "clk_periph_mmc", CLK_AHB, 3, 0),
134 CLK_PERIPH(CLK_TIMER, "clk_periph_timer", CLK_RTCREF, 4, 0),
135 CLK_PERIPH(CLK_MMUART0, "clk_periph_mmuart0", CLK_AHB, 5, CLK_IS_CRITICAL),
136 CLK_PERIPH(CLK_MMUART1, "clk_periph_mmuart1", CLK_AHB, 6, 0),
137 CLK_PERIPH(CLK_MMUART2, "clk_periph_mmuart2", CLK_AHB, 7, 0),
138 CLK_PERIPH(CLK_MMUART3, "clk_periph_mmuart3", CLK_AHB, 8, 0),
139 CLK_PERIPH(CLK_MMUART4, "clk_periph_mmuart4", CLK_AHB, 9, 0),
140 CLK_PERIPH(CLK_SPI0, "clk_periph_spi0", CLK_AHB, 10, 0),
141 CLK_PERIPH(CLK_SPI1, "clk_periph_spi1", CLK_AHB, 11, 0),
142 CLK_PERIPH(CLK_I2C0, "clk_periph_i2c0", CLK_AHB, 12, 0),
143 CLK_PERIPH(CLK_I2C1, "clk_periph_i2c1", CLK_AHB, 13, 0),
144 CLK_PERIPH(CLK_CAN0, "clk_periph_can0", CLK_AHB, 14, 0),
145 CLK_PERIPH(CLK_CAN1, "clk_periph_can1", CLK_AHB, 15, 0),
146 CLK_PERIPH(CLK_USB, "clk_periph_usb", CLK_AHB, 16, 0),
147 CLK_PERIPH(CLK_RTC, "clk_periph_rtc", CLK_AHB, 18, CLK_IS_CRITICAL),
148 CLK_PERIPH(CLK_QSPI, "clk_periph_qspi", CLK_AHB, 19, 0),
149 CLK_PERIPH(CLK_GPIO0, "clk_periph_gpio0", CLK_AHB, 20, 0),
150 CLK_PERIPH(CLK_GPIO1, "clk_periph_gpio1", CLK_AHB, 21, 0),
151 CLK_PERIPH(CLK_GPIO2, "clk_periph_gpio2", CLK_AHB, 22, 0),
152 CLK_PERIPH(CLK_DDRC, "clk_periph_ddrc", CLK_AHB, 23, CLK_IS_CRITICAL),
153 CLK_PERIPH(CLK_FIC0, "clk_periph_fic0", CLK_AXI, 24, CLK_IS_CRITICAL),
154 CLK_PERIPH(CLK_FIC1, "clk_periph_fic1", CLK_AXI, 25, CLK_IS_CRITICAL),
155 CLK_PERIPH(CLK_FIC2, "clk_periph_fic2", CLK_AXI, 26, CLK_IS_CRITICAL),
156 CLK_PERIPH(CLK_FIC3, "clk_periph_fic3", CLK_AXI, 27, CLK_IS_CRITICAL),
157 CLK_PERIPH(CLK_ATHENA, "clk_periph_athena", CLK_AXI, 28, CLK_IS_CRITICAL),
158 CLK_PERIPH(CLK_CFM, "clk_periph_cfm", CLK_AHB, 29, 0),
159 };
160
mpfs_clk_register_periphs(struct udevice * dev,struct regmap * regmap)161 int mpfs_clk_register_periphs(struct udevice *dev, struct regmap *regmap)
162 {
163 int ret;
164 int i, id, num_clks;
165 const char *name;
166 struct clk *hw;
167
168 num_clks = ARRAY_SIZE(mpfs_periph_clks);
169 for (i = 0; i < num_clks; i++) {
170 struct clk parent = { .id = mpfs_periph_clks[i].periph.parent_id };
171
172 clk_request(dev, &parent);
173 hw = &mpfs_periph_clks[i].hw;
174 mpfs_periph_clks[i].regmap = regmap;
175 mpfs_periph_clks[i].prate = clk_get_rate(&parent);
176 name = mpfs_periph_clks[i].periph.name;
177 ret = clk_register(hw, MPFS_PERIPH_CLOCK, name, parent.dev->name);
178 if (ret)
179 ERR_PTR(ret);
180 id = mpfs_periph_clks[i].periph.id;
181 clk_dm(id, hw);
182 }
183
184 return 0;
185 }
186
187 const struct clk_ops mpfs_periph_clk_ops = {
188 .enable = mpfs_periph_clk_enable,
189 .disable = mpfs_periph_clk_disable,
190 .get_rate = mpfs_periph_clk_recalc_rate,
191 };
192
193 U_BOOT_DRIVER(mpfs_periph_clock) = {
194 .name = MPFS_PERIPH_CLOCK,
195 .id = UCLASS_CLK,
196 .ops = &mpfs_periph_clk_ops,
197 };
198