1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Clock drivers for Qualcomm IPQ40xx
4 *
5 * Copyright (c) 2020 Sartura Ltd.
6 *
7 * Author: Robert Marko <robert.marko@sartura.hr>
8 *
9 */
10
11 #include <clk-uclass.h>
12 #include <dm.h>
13 #include <errno.h>
14 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
15
16 #include "clock-qcom.h"
17
18 /* I2C controller clock control registerss */
19 #define BLSP1_QUP1_I2C_APPS_CBCR (0x2008)
20 #define BLSP1_QUP1_I2C_APPS_CMD_RCGR (0x200C)
21 #define BLSP1_QUP2_I2C_APPS_CBCR (0x3010)
22 #define BLSP1_QUP2_I2C_APPS_CMD_RCGR (0x3000)
23
ipq4019_clk_set_rate(struct clk * clk,ulong rate)24 static ulong ipq4019_clk_set_rate(struct clk *clk, ulong rate)
25 {
26 switch (clk->id) {
27 case GCC_BLSP1_UART1_APPS_CLK: /*UART1*/
28 /* This clock is already initialized by SBL1 */
29 return 1843200;
30 default:
31 return -EINVAL;
32 }
33 }
34
ipq4019_clk_enable(struct clk * clk)35 static int ipq4019_clk_enable(struct clk *clk)
36 {
37 struct msm_clk_priv *priv = dev_get_priv(clk->dev);
38
39 switch (clk->id) {
40 case GCC_BLSP1_AHB_CLK:
41 /* This clock is already initialized by SBL1 */
42 return 0;
43 case GCC_BLSP1_QUP1_I2C_APPS_CLK:
44 clk_enable_cbc(priv->base + BLSP1_QUP1_I2C_APPS_CBCR);
45 clk_rcg_set_rate(priv->base, BLSP1_QUP1_I2C_APPS_CMD_RCGR, 0,
46 CFG_CLK_SRC_CXO);
47 return 0;
48 case GCC_BLSP1_QUP2_I2C_APPS_CLK:
49 clk_enable_cbc(priv->base + BLSP1_QUP2_I2C_APPS_CBCR);
50 clk_rcg_set_rate(priv->base, BLSP1_QUP2_I2C_APPS_CMD_RCGR, 0,
51 CFG_CLK_SRC_CXO);
52 return 0;
53 case GCC_BLSP1_QUP1_SPI_APPS_CLK: /*SPI1*/
54 /* This clock is already initialized by SBL1 */
55 return 0;
56 case GCC_PRNG_AHB_CLK: /*PRNG*/
57 /* This clock is already initialized by SBL1 */
58 return 0;
59 case GCC_USB3_MASTER_CLK:
60 case GCC_USB3_SLEEP_CLK:
61 case GCC_USB3_MOCK_UTMI_CLK:
62 case GCC_USB2_MASTER_CLK:
63 case GCC_USB2_SLEEP_CLK:
64 case GCC_USB2_MOCK_UTMI_CLK:
65 /* These clocks is already initialized by SBL1 */
66 return 0;
67 case GCC_ESS_CLK:
68 /* This clock is already initialized by SBL1 */
69 return 0;
70 default:
71 return -EINVAL;
72 }
73 }
74
75 static const struct qcom_reset_map gcc_ipq4019_resets[] = {
76 [WIFI0_CPU_INIT_RESET] = { 0x1f008, 5 },
77 [WIFI0_RADIO_SRIF_RESET] = { 0x1f008, 4 },
78 [WIFI0_RADIO_WARM_RESET] = { 0x1f008, 3 },
79 [WIFI0_RADIO_COLD_RESET] = { 0x1f008, 2 },
80 [WIFI0_CORE_WARM_RESET] = { 0x1f008, 1 },
81 [WIFI0_CORE_COLD_RESET] = { 0x1f008, 0 },
82 [WIFI1_CPU_INIT_RESET] = { 0x20008, 5 },
83 [WIFI1_RADIO_SRIF_RESET] = { 0x20008, 4 },
84 [WIFI1_RADIO_WARM_RESET] = { 0x20008, 3 },
85 [WIFI1_RADIO_COLD_RESET] = { 0x20008, 2 },
86 [WIFI1_CORE_WARM_RESET] = { 0x20008, 1 },
87 [WIFI1_CORE_COLD_RESET] = { 0x20008, 0 },
88 [USB3_UNIPHY_PHY_ARES] = { 0x1e038, 5 },
89 [USB3_HSPHY_POR_ARES] = { 0x1e038, 4 },
90 [USB3_HSPHY_S_ARES] = { 0x1e038, 2 },
91 [USB2_HSPHY_POR_ARES] = { 0x1e01c, 4 },
92 [USB2_HSPHY_S_ARES] = { 0x1e01c, 2 },
93 [PCIE_PHY_AHB_ARES] = { 0x1d010, 11 },
94 [PCIE_AHB_ARES] = { 0x1d010, 10 },
95 [PCIE_PWR_ARES] = { 0x1d010, 9 },
96 [PCIE_PIPE_STICKY_ARES] = { 0x1d010, 8 },
97 [PCIE_AXI_M_STICKY_ARES] = { 0x1d010, 7 },
98 [PCIE_PHY_ARES] = { 0x1d010, 6 },
99 [PCIE_PARF_XPU_ARES] = { 0x1d010, 5 },
100 [PCIE_AXI_S_XPU_ARES] = { 0x1d010, 4 },
101 [PCIE_AXI_M_VMIDMT_ARES] = { 0x1d010, 3 },
102 [PCIE_PIPE_ARES] = { 0x1d010, 2 },
103 [PCIE_AXI_S_ARES] = { 0x1d010, 1 },
104 [PCIE_AXI_M_ARES] = { 0x1d010, 0 },
105 [ESS_RESET] = { 0x12008, 0},
106 [GCC_BLSP1_BCR] = {0x01000, 0},
107 [GCC_BLSP1_QUP1_BCR] = {0x02000, 0},
108 [GCC_BLSP1_UART1_BCR] = {0x02038, 0},
109 [GCC_BLSP1_QUP2_BCR] = {0x03008, 0},
110 [GCC_BLSP1_UART2_BCR] = {0x03028, 0},
111 [GCC_BIMC_BCR] = {0x04000, 0},
112 [GCC_TLMM_BCR] = {0x05000, 0},
113 [GCC_IMEM_BCR] = {0x0E000, 0},
114 [GCC_ESS_BCR] = {0x12008, 0},
115 [GCC_PRNG_BCR] = {0x13000, 0},
116 [GCC_BOOT_ROM_BCR] = {0x13008, 0},
117 [GCC_CRYPTO_BCR] = {0x16000, 0},
118 [GCC_SDCC1_BCR] = {0x18000, 0},
119 [GCC_SEC_CTRL_BCR] = {0x1A000, 0},
120 [GCC_AUDIO_BCR] = {0x1B008, 0},
121 [GCC_QPIC_BCR] = {0x1C000, 0},
122 [GCC_PCIE_BCR] = {0x1D000, 0},
123 [GCC_USB2_BCR] = {0x1E008, 0},
124 [GCC_USB2_PHY_BCR] = {0x1E018, 0},
125 [GCC_USB3_BCR] = {0x1E024, 0},
126 [GCC_USB3_PHY_BCR] = {0x1E034, 0},
127 [GCC_SYSTEM_NOC_BCR] = {0x21000, 0},
128 [GCC_PCNOC_BCR] = {0x2102C, 0},
129 [GCC_DCD_BCR] = {0x21038, 0},
130 [GCC_SNOC_BUS_TIMEOUT0_BCR] = {0x21064, 0},
131 [GCC_SNOC_BUS_TIMEOUT1_BCR] = {0x2106C, 0},
132 [GCC_SNOC_BUS_TIMEOUT2_BCR] = {0x21074, 0},
133 [GCC_SNOC_BUS_TIMEOUT3_BCR] = {0x2107C, 0},
134 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = {0x21084, 0},
135 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = {0x2108C, 0},
136 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = {0x21094, 0},
137 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = {0x2109C, 0},
138 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = {0x210A4, 0},
139 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = {0x210AC, 0},
140 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = {0x210B4, 0},
141 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = {0x210BC, 0},
142 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = {0x210C4, 0},
143 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = {0x210CC, 0},
144 [GCC_TCSR_BCR] = {0x22000, 0},
145 [GCC_MPM_BCR] = {0x24000, 0},
146 [GCC_SPDM_BCR] = {0x25000, 0},
147 [ESS_MAC1_ARES] = {0x1200C, 0},
148 [ESS_MAC2_ARES] = {0x1200C, 1},
149 [ESS_MAC3_ARES] = {0x1200C, 2},
150 [ESS_MAC4_ARES] = {0x1200C, 3},
151 [ESS_MAC5_ARES] = {0x1200C, 4},
152 [ESS_PSGMII_ARES] = {0x1200C, 5},
153 };
154
155 static struct msm_clk_data ipq4019_clk_data = {
156 .enable = ipq4019_clk_enable,
157 .set_rate = ipq4019_clk_set_rate,
158 .resets = gcc_ipq4019_resets,
159 .num_resets = ARRAY_SIZE(gcc_ipq4019_resets),
160 };
161
162 static const struct udevice_id gcc_ipq4019_of_match[] = {
163 {
164 .compatible = "qcom,gcc-ipq4019",
165 .data = (ulong)&ipq4019_clk_data,
166 },
167 { }
168 };
169
170 U_BOOT_DRIVER(gcc_ipq4019) = {
171 .name = "gcc_ipq4019",
172 .id = UCLASS_NOP,
173 .of_match = gcc_ipq4019_of_match,
174 .bind = qcom_cc_bind,
175 .flags = DM_FLAG_PRE_RELOC,
176 };
177