1 // SPDX-License-Identifier: BSD-3-Clause AND GPL-2.0
2 /*
3 * Clock and reset drivers for Qualcomm platforms Global Clock
4 * Controller (GCC).
5 *
6 * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
7 * (C) Copyright 2020 Sartura Ltd. (reset driver)
8 * Author: Robert Marko <robert.marko@sartura.hr>
9 * (C) Copyright 2022 Linaro Ltd. (reset driver)
10 * Author: Sumit Garg <sumit.garg@linaro.org>
11 *
12 * Based on Little Kernel driver, simplified
13 */
14
15 #include <clk-uclass.h>
16 #include <linux/clk-provider.h>
17 #include <dm.h>
18 #include <dm/device-internal.h>
19 #include <dm/lists.h>
20 #include <errno.h>
21 #include <asm/io.h>
22 #include <linux/bug.h>
23 #include <linux/delay.h>
24 #include <linux/bitops.h>
25 #include <linux/iopoll.h>
26 #include <reset-uclass.h>
27 #include <power-domain-uclass.h>
28
29 #include "clock-qcom.h"
30
31 /* CBCR register fields */
32 #define CBCR_BRANCH_ENABLE_BIT BIT(0)
33 #define CBCR_BRANCH_OFF_BIT BIT(31)
34
35 #define GDSC_SW_COLLAPSE_MASK BIT(0)
36 #define GDSC_POWER_DOWN_COMPLETE BIT(15)
37 #define GDSC_POWER_UP_COMPLETE BIT(16)
38 #define GDSC_PWR_ON_MASK BIT(31)
39 #define CFG_GDSCR_OFFSET 0x4
40 #define GDSC_STATUS_POLL_TIMEOUT_US 1500
41
42 /* Enable clock controlled by CBC soft macro */
clk_enable_cbc(phys_addr_t cbcr)43 void clk_enable_cbc(phys_addr_t cbcr)
44 {
45 setbits_le32(cbcr, CBCR_BRANCH_ENABLE_BIT);
46
47 while (readl(cbcr) & CBCR_BRANCH_OFF_BIT)
48 ;
49 }
50
clk_enable_gpll0(phys_addr_t base,const struct pll_vote_clk * gpll0)51 void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0)
52 {
53 if (readl(base + gpll0->status) & gpll0->status_bit)
54 return; /* clock already enabled */
55
56 setbits_le32(base + gpll0->ena_vote, gpll0->vote_bit);
57
58 while ((readl(base + gpll0->status) & gpll0->status_bit) == 0)
59 ;
60 }
61
62 #define BRANCH_ON_VAL (0)
63 #define BRANCH_NOC_FSM_ON_VAL BIT(29)
64 #define BRANCH_CHECK_MASK GENMASK(31, 28)
65
clk_enable_vote_clk(phys_addr_t base,const struct vote_clk * vclk)66 void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk)
67 {
68 u32 val;
69
70 setbits_le32(base + vclk->ena_vote, vclk->vote_bit);
71 do {
72 val = readl(base + vclk->cbcr_reg);
73 val &= BRANCH_CHECK_MASK;
74 } while ((val != BRANCH_ON_VAL) && (val != BRANCH_NOC_FSM_ON_VAL));
75 }
76
qcom_gate_clk_en(const struct msm_clk_priv * priv,unsigned long id)77 int qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id)
78 {
79 if (id >= priv->data->num_clks || priv->data->clks[id].reg == 0) {
80 log_err("gcc@%#08llx: unknown clock ID %lu!\n",
81 priv->base, id);
82 return -ENOENT;
83 }
84
85 setbits_le32(priv->base + priv->data->clks[id].reg, priv->data->clks[id].en_val);
86 if (priv->data->clks[id].cbcr_reg) {
87 unsigned int count;
88 u32 val;
89
90 for (count = 0; count < 200; count++) {
91 val = readl(priv->base + priv->data->clks[id].cbcr_reg);
92 val &= BRANCH_CHECK_MASK;
93 if (val == BRANCH_ON_VAL || val == BRANCH_NOC_FSM_ON_VAL)
94 break;
95 udelay(1);
96 }
97 if (WARN(count == 200, "WARNING: Clock @ %#lx [%#010x] stuck at off\n",
98 priv->data->clks[id].cbcr_reg, val))
99 return -EBUSY;
100 }
101 return 0;
102 }
103
104 #define APPS_CMD_RCGR_UPDATE BIT(0)
105
106 /* Update clock command via CMD_RCGR */
clk_bcr_update(phys_addr_t apps_cmd_rcgr)107 void clk_bcr_update(phys_addr_t apps_cmd_rcgr)
108 {
109 u32 count;
110 setbits_le32(apps_cmd_rcgr, APPS_CMD_RCGR_UPDATE);
111
112 /* Wait for frequency to be updated. */
113 for (count = 0; count < 50000; count++) {
114 if (!(readl(apps_cmd_rcgr) & APPS_CMD_RCGR_UPDATE))
115 break;
116 udelay(1);
117 }
118 WARN(count == 50000, "WARNING: RCG @ %#llx [%#010x] stuck at off\n",
119 apps_cmd_rcgr, readl(apps_cmd_rcgr));
120 }
121
122 #define CFG_SRC_DIV_MASK 0b11111
123 #define CFG_SRC_SEL_SHIFT 8
124 #define CFG_SRC_SEL_MASK (0x7 << CFG_SRC_SEL_SHIFT)
125 #define CFG_MODE_SHIFT 12
126 #define CFG_MODE_MASK (0x3 << CFG_MODE_SHIFT)
127 #define CFG_MODE_DUAL_EDGE (0x2 << CFG_MODE_SHIFT)
128 #define CFG_HW_CLK_CTRL_MASK BIT(20)
129
130 /*
131 * root set rate for clocks with half integer and MND divider
132 * div should be pre-calculated ((div * 2) - 1)
133 */
clk_rcg_set_rate_mnd(phys_addr_t base,uint32_t cmd_rcgr,int div,int m,int n,int source,u8 mnd_width)134 void clk_rcg_set_rate_mnd(phys_addr_t base, uint32_t cmd_rcgr,
135 int div, int m, int n, int source, u8 mnd_width)
136 {
137 u32 cfg;
138 /* M value for MND divider. */
139 u32 m_val = m;
140 u32 n_minus_m = n - m;
141 /* NOT(N-M) value for MND divider. */
142 u32 n_val = ~n_minus_m * !!(n);
143 /* NOT 2D value for MND divider. */
144 u32 d_val = ~(clamp_t(u32, n, m, n_minus_m));
145 u32 mask = BIT(mnd_width) - 1;
146
147 debug("m %#x n %#x d %#x div %#x mask %#x\n", m_val, n_val, d_val, div, mask);
148
149 /* Program MND values */
150 writel(m_val & mask, base + cmd_rcgr + RCG_M_REG);
151 writel(n_val & mask, base + cmd_rcgr + RCG_N_REG);
152 writel(d_val & mask, base + cmd_rcgr + RCG_D_REG);
153
154 /* setup src select and divider */
155 cfg = readl(base + cmd_rcgr + RCG_CFG_REG);
156 cfg &= ~(CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK |
157 CFG_SRC_DIV_MASK);
158 cfg |= source & CFG_SRC_SEL_MASK; /* Select clock source */
159
160 if (div)
161 cfg |= div & CFG_SRC_DIV_MASK;
162
163 if (n && n != m)
164 cfg |= CFG_MODE_DUAL_EDGE;
165
166 writel(cfg, base + cmd_rcgr + RCG_CFG_REG); /* Write new clock configuration */
167
168 /* Inform h/w to start using the new config. */
169 clk_bcr_update(base + cmd_rcgr);
170 }
171
172 /* root set rate for clocks with half integer and mnd_width=0 */
clk_rcg_set_rate(phys_addr_t base,uint32_t cmd_rcgr,int div,int source)173 void clk_rcg_set_rate(phys_addr_t base, uint32_t cmd_rcgr, int div,
174 int source)
175 {
176 u32 cfg;
177
178 /* setup src select and divider */
179 cfg = readl(base + cmd_rcgr + RCG_CFG_REG);
180 cfg &= ~(CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK);
181 cfg |= source & CFG_CLK_SRC_MASK; /* Select clock source */
182
183 /*
184 * Set the divider; HW permits fraction dividers (+0.5), but
185 * for simplicity, we will support integers only
186 */
187 if (div)
188 cfg |= (2 * div - 1) & CFG_SRC_DIV_MASK;
189
190 writel(cfg, base + cmd_rcgr + RCG_CFG_REG); /* Write new clock configuration */
191
192 /* Inform h/w to start using the new config. */
193 clk_bcr_update(base + cmd_rcgr);
194 }
195
196 #define PHY_MUX_MASK GENMASK(1, 0)
197 #define PHY_MUX_PHY_SRC 0
198 #define PHY_MUX_REF_SRC 2
199
clk_phy_mux_enable(phys_addr_t base,uint32_t cmd_rcgr,bool enabled)200 void clk_phy_mux_enable(phys_addr_t base, uint32_t cmd_rcgr, bool enabled)
201 {
202 u32 cfg;
203
204 /* setup src select and divider */
205 cfg = readl(base + cmd_rcgr);
206 cfg &= ~(PHY_MUX_MASK);
207 if (enabled)
208 cfg |= FIELD_PREP(PHY_MUX_MASK, PHY_MUX_PHY_SRC);
209 else
210 cfg |= FIELD_PREP(PHY_MUX_MASK, PHY_MUX_REF_SRC);
211
212 writel(cfg, base + cmd_rcgr);
213 }
214
qcom_find_freq(const struct freq_tbl * f,uint rate)215 const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate)
216 {
217 if (!f)
218 return NULL;
219
220 if (!f->freq)
221 return f;
222
223 for (; f->freq; f++)
224 if (rate <= f->freq)
225 return f;
226
227 /* Default to our fastest rate */
228 return f - 1;
229 }
230
msm_clk_probe(struct udevice * dev)231 static int msm_clk_probe(struct udevice *dev)
232 {
233 struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(dev);
234 struct msm_clk_priv *priv = dev_get_priv(dev);
235
236 priv->base = dev_read_addr(dev);
237 if (priv->base == FDT_ADDR_T_NONE)
238 return -EINVAL;
239
240 priv->data = data;
241
242 return 0;
243 }
244
msm_clk_set_rate(struct clk * clk,ulong rate)245 static ulong msm_clk_set_rate(struct clk *clk, ulong rate)
246 {
247 struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(clk->dev);
248
249 if (data->set_rate)
250 return data->set_rate(clk, rate);
251
252 return 0;
253 }
254
msm_clk_enable(struct clk * clk)255 static int msm_clk_enable(struct clk *clk)
256 {
257 struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(clk->dev);
258
259 if (data->enable)
260 return data->enable(clk);
261
262 return 0;
263 }
264
dump_gplls(struct udevice * dev,phys_addr_t base)265 static void dump_gplls(struct udevice *dev, phys_addr_t base)
266 {
267 struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(dev);
268 u32 i;
269 bool locked;
270 u64 l, a, xo_rate = 19200000;
271 struct clk *clk = NULL;
272 struct udevice *xodev;
273 const phys_addr_t *gplls = data->dbg_pll_addrs;
274
275 uclass_foreach_dev_probe(UCLASS_CLK, xodev) {
276 if (!strcmp(xodev->name, "xo-board") || !strcmp(xodev->name, "xo_board")) {
277 clk = dev_get_clk_ptr(xodev);
278 break;
279 }
280 }
281
282 if (clk) {
283 xo_rate = clk_get_rate(clk);
284
285 /* On SDM845 this needs to be divided by 2 for some reason */
286 if (xo_rate && of_machine_is_compatible("qcom,sdm845"))
287 xo_rate /= 2;
288 } else {
289 printf("Can't find XO clock, XO_BOARD rate may be wrong\n");
290 }
291
292 printf("GPLL clocks:\n");
293 printf("| GPLL | LOCKED | XO_BOARD | PLL_L | ALPHA |\n");
294 printf("+--------+--------+-----------+------------+----------------+\n");
295 for (i = 0; i < data->num_plls; i++) {
296 locked = !!(readl(gplls[i]) & BIT(31));
297 l = readl(gplls[i] + 4) & (BIT(16) - 1);
298 a = readq(gplls[i] + 40) & (BIT(16) - 1);
299 printf("| GPLL%-2d | %-6s | %9llu * (%#-9llx + %#-13llx * 2 ** -40 ) / 1000000\n",
300 i, locked ? "X" : "", xo_rate, l, a);
301 }
302 }
303
dump_rcgs(struct udevice * dev)304 static void dump_rcgs(struct udevice *dev)
305 {
306 struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(dev);
307 int i;
308 u32 cmd;
309 u32 cfg;
310 u32 not_n_minus_m;
311 u32 src, m, n, div;
312 bool root_on, d_odd;
313
314 printf("\nRCGs:\n");
315
316 /*
317 * Which GPLL SRC corresponds to depends on the parent map, see gcc-<soc>.c in Linux
318 * and find the parent map associated with the clock. Note that often there are multiple
319 * outputs from a single GPLL where one is actually half the rate of the other (_EVEN).
320 * intput_freq = associated GPLL output freq (potentially divided depending on SRC).
321 */
322 printf("| NAME | ON | SRC | OUT_FREQ = input_freq * (m/n) * (1/d) | [CMD REG ] |\n");
323 printf("+----------------------------------+----+-----+---------------------------------------+--------------+\n");
324 for (i = 0; i < data->num_rcgs; i++) {
325 cmd = readl(data->dbg_rcg_addrs[i]);
326 cfg = readl(data->dbg_rcg_addrs[i] + 0x4);
327 m = readl(data->dbg_rcg_addrs[i] + 0x8);
328 n = 0;
329 not_n_minus_m = readl(data->dbg_rcg_addrs[i] + 0xc);
330
331 root_on = !(cmd & BIT(31)); // ROOT_OFF
332 src = (cfg >> 8) & 7;
333
334 if (not_n_minus_m) {
335 n = (~not_n_minus_m & 0xffff);
336
337 /* A clumsy assumption that this is an 8-bit MND RCG */
338 if ((n & 0xff00) == 0xff00)
339 n = n & 0xff;
340
341 n += m;
342 }
343
344 div = ((cfg & 0b11111) + 1) / 2;
345 d_odd = ((cfg & 0b11111) + 1) % 2 == 1;
346 printf("%-34s | %-2s | %3d | input_freq * (%4d/%5d) * (1/%1d%-2s) | [%#010x]\n",
347 data->dbg_rcg_names[i], root_on ? "X" : "", src,
348 m ?: 1, n ?: 1, div, d_odd ? ".5" : "", cmd);
349 }
350
351 printf("\n");
352 }
353
msm_dump_clks(struct udevice * dev)354 static void __maybe_unused msm_dump_clks(struct udevice *dev)
355 {
356 struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(dev);
357 struct msm_clk_priv *priv = dev_get_priv(dev);
358 const struct gate_clk *sclk;
359 int val, i;
360
361 if (!data->clks) {
362 printf("No clocks\n");
363 return;
364 }
365
366 printf("Gate Clocks:\n");
367 for (i = 0; i < data->num_clks; i++) {
368 sclk = &data->clks[i];
369 if (!sclk->name)
370 continue;
371 printf("%-32s: ", sclk->name);
372 val = readl(priv->base + sclk->reg) & sclk->en_val;
373 printf("%s\n", val ? "ON" : "");
374 }
375
376 dump_gplls(dev, priv->base);
377 dump_rcgs(dev);
378 }
379
380 static struct clk_ops msm_clk_ops = {
381 .set_rate = msm_clk_set_rate,
382 .enable = msm_clk_enable,
383 #if IS_ENABLED(CONFIG_CMD_CLK)
384 .dump = msm_dump_clks,
385 #endif
386 };
387
388 U_BOOT_DRIVER(qcom_clk) = {
389 .name = "qcom_clk",
390 .id = UCLASS_CLK,
391 .ops = &msm_clk_ops,
392 .priv_auto = sizeof(struct msm_clk_priv),
393 .probe = msm_clk_probe,
394 .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF,
395 };
396
qcom_cc_bind(struct udevice * parent)397 int qcom_cc_bind(struct udevice *parent)
398 {
399 struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(parent);
400 struct udevice *clkdev = NULL, *rstdev = NULL, *pwrdev;
401 struct driver *drv;
402 int ret;
403
404 /* Get a handle to the common clk handler */
405 drv = lists_driver_lookup_name("qcom_clk");
406 if (!drv)
407 return -ENOENT;
408
409 /* Register the clock controller */
410 ret = device_bind_with_driver_data(parent, drv, "qcom_clk", (ulong)data,
411 dev_ofnode(parent), &clkdev);
412 if (ret)
413 return ret;
414
415 if (data->resets) {
416 /* Get a handle to the common reset handler */
417 drv = lists_driver_lookup_name("qcom_reset");
418 if (!drv) {
419 ret = -ENOENT;
420 goto unbind_clkdev;
421 }
422
423 /* Register the reset controller */
424 ret = device_bind_with_driver_data(parent, drv, "qcom_reset", (ulong)data,
425 dev_ofnode(parent), &rstdev);
426 if (ret)
427 goto unbind_clkdev;
428 }
429
430 if (data->power_domains) {
431 /* Get a handle to the common power domain handler */
432 drv = lists_driver_lookup_name("qcom_power");
433 if (!drv) {
434 ret = -ENOENT;
435 goto unbind_rstdev;
436 }
437 /* Register the power domain controller */
438 ret = device_bind_with_driver_data(parent, drv, "qcom_power", (ulong)data,
439 dev_ofnode(parent), &pwrdev);
440 if (ret)
441 goto unbind_rstdev;
442 }
443
444 return 0;
445
446 unbind_rstdev:
447 device_unbind(rstdev);
448 unbind_clkdev:
449 device_unbind(clkdev);
450
451 return ret;
452 }
453
qcom_reset_set(struct reset_ctl * rst,bool assert)454 static int qcom_reset_set(struct reset_ctl *rst, bool assert)
455 {
456 struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(rst->dev);
457 void __iomem *base = dev_get_priv(rst->dev);
458 const struct qcom_reset_map *map;
459 u32 value;
460
461 map = &data->resets[rst->id];
462
463 value = readl(base + map->reg);
464
465 if (assert)
466 value |= BIT(map->bit);
467 else
468 value &= ~BIT(map->bit);
469
470 writel(value, base + map->reg);
471
472 return 0;
473 }
474
qcom_reset_assert(struct reset_ctl * rst)475 static int qcom_reset_assert(struct reset_ctl *rst)
476 {
477 return qcom_reset_set(rst, true);
478 }
479
qcom_reset_deassert(struct reset_ctl * rst)480 static int qcom_reset_deassert(struct reset_ctl *rst)
481 {
482 return qcom_reset_set(rst, false);
483 }
484
485 static const struct reset_ops qcom_reset_ops = {
486 .rst_assert = qcom_reset_assert,
487 .rst_deassert = qcom_reset_deassert,
488 };
489
qcom_reset_probe(struct udevice * dev)490 static int qcom_reset_probe(struct udevice *dev)
491 {
492 /* Set our priv pointer to the base address */
493 dev_set_priv(dev, (void *)dev_read_addr(dev));
494
495 return 0;
496 }
497
498 U_BOOT_DRIVER(qcom_reset) = {
499 .name = "qcom_reset",
500 .id = UCLASS_RESET,
501 .ops = &qcom_reset_ops,
502 .probe = qcom_reset_probe,
503 };
504
qcom_power_set(struct power_domain * pwr,bool on)505 static int qcom_power_set(struct power_domain *pwr, bool on)
506 {
507 struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(pwr->dev);
508 void __iomem *base = dev_get_priv(pwr->dev);
509 const struct qcom_power_map *map;
510 u32 value;
511 int ret;
512
513 if (pwr->id >= data->num_power_domains)
514 return -ENODEV;
515
516 map = &data->power_domains[pwr->id];
517
518 if (!map->reg)
519 return -ENODEV;
520
521 value = readl(base + map->reg);
522
523 if (on)
524 value &= ~GDSC_SW_COLLAPSE_MASK;
525 else
526 value |= GDSC_SW_COLLAPSE_MASK;
527
528 writel(value, base + map->reg);
529
530 if (on)
531 ret = readl_poll_timeout(base + map->reg + CFG_GDSCR_OFFSET,
532 value,
533 (value & GDSC_POWER_UP_COMPLETE) ||
534 (value & GDSC_PWR_ON_MASK),
535 GDSC_STATUS_POLL_TIMEOUT_US);
536
537 else
538 ret = readl_poll_timeout(base + map->reg + CFG_GDSCR_OFFSET,
539 value,
540 (value & GDSC_POWER_DOWN_COMPLETE) ||
541 !(value & GDSC_PWR_ON_MASK),
542 GDSC_STATUS_POLL_TIMEOUT_US);
543
544 if (ret == -ETIMEDOUT)
545 printf("WARNING: GDSC %lu is stuck during power on/off\n",
546 pwr->id);
547 return ret;
548 }
549
qcom_power_on(struct power_domain * pwr)550 static int qcom_power_on(struct power_domain *pwr)
551 {
552 return qcom_power_set(pwr, true);
553 }
554
qcom_power_off(struct power_domain * pwr)555 static int qcom_power_off(struct power_domain *pwr)
556 {
557 return qcom_power_set(pwr, false);
558 }
559
560 static const struct power_domain_ops qcom_power_ops = {
561 .on = qcom_power_on,
562 .off = qcom_power_off,
563 };
564
qcom_power_probe(struct udevice * dev)565 static int qcom_power_probe(struct udevice *dev)
566 {
567 /* Set our priv pointer to the base address */
568 dev_set_priv(dev, (void *)dev_read_addr(dev));
569
570 return 0;
571 }
572
573 U_BOOT_DRIVER(qcom_power) = {
574 .name = "qcom_power",
575 .id = UCLASS_POWER_DOMAIN,
576 .ops = &qcom_power_ops,
577 .probe = qcom_power_probe,
578 .flags = DM_FLAG_PRE_RELOC,
579 };
580