1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> 4 */ 5 #ifndef _CLOCK_QCOM_H 6 #define _CLOCK_QCOM_H 7 8 #include <asm/io.h> 9 #include <linux/bitfield.h> 10 #include <errno.h> 11 12 #define CFG_CLK_SRC_CXO (0 << 8) 13 #define CFG_CLK_SRC_GPLL0 (1 << 8) 14 #define CFG_CLK_SRC_GPLL0_AUX2 (2 << 8) 15 #define CFG_CLK_SRC_GPLL2 (2 << 8) 16 #define CFG_CLK_SRC_GPLL2_MAIN (2 << 8) 17 #define CFG_CLK_SRC_GPLL9 (2 << 8) 18 #define CFG_CLK_SRC_GPLL0_ODD (3 << 8) 19 #define CFG_CLK_SRC_GPLL6 (4 << 8) 20 #define CFG_CLK_SRC_GPLL7 (3 << 8) 21 #define CFG_CLK_SRC_GPLL4 (5 << 8) 22 #define CFG_CLK_SRC_GPLL0_EVEN (6 << 8) 23 #define CFG_CLK_SRC_MASK (7 << 8) 24 25 #define RCG_CFG_REG 0x4 26 #define RCG_M_REG 0x8 27 #define RCG_N_REG 0xc 28 #define RCG_D_REG 0x10 29 30 struct pll_vote_clk { 31 uintptr_t status; 32 int status_bit; 33 uintptr_t ena_vote; 34 int vote_bit; 35 }; 36 37 struct vote_clk { 38 uintptr_t cbcr_reg; 39 uintptr_t ena_vote; 40 int vote_bit; 41 }; 42 43 struct freq_tbl { 44 uint freq; 45 uint src; 46 u8 pre_div; 47 u16 m; 48 u16 n; 49 }; 50 51 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } 52 53 struct gate_clk { 54 uintptr_t reg; 55 u32 en_val; 56 uintptr_t cbcr_reg; 57 const char *name; 58 }; 59 60 /* 61 * GATE_CLK() is deprecated: Use GATE_CLK_POLLED() instead to ensure the clock 62 * is running before we start making use of devices or registers. 63 */ 64 #ifdef DEBUG 65 #define GATE_CLK(clk, reg, val) [clk] = { reg, val, 0, #clk } 66 #define GATE_CLK_POLLED(clk, en_reg, val, cbcr_reg) [clk] = { en_reg, val, cbcr_reg, #clk } 67 #else 68 #define GATE_CLK(clk, reg, val) [clk] = { reg, val, 0, NULL } 69 #define GATE_CLK_POLLED(clk, en_reg, val, cbcr_reg) [clk] = { en_reg, val, cbcr_reg, NULL } 70 #endif 71 72 struct qcom_reset_map { 73 unsigned int reg; 74 u8 bit; 75 }; 76 77 struct qcom_power_map { 78 unsigned int reg; 79 }; 80 81 struct clk; 82 83 struct msm_clk_data { 84 const struct qcom_power_map *power_domains; 85 unsigned long num_power_domains; 86 const struct qcom_reset_map *resets; 87 unsigned long num_resets; 88 const struct gate_clk *clks; 89 unsigned long num_clks; 90 91 const phys_addr_t *dbg_pll_addrs; 92 unsigned long num_plls; 93 const phys_addr_t *dbg_rcg_addrs; 94 unsigned long num_rcgs; 95 const char * const *dbg_rcg_names; 96 97 int (*enable)(struct clk *clk); 98 unsigned long (*set_rate)(struct clk *clk, unsigned long rate); 99 }; 100 101 struct msm_clk_priv { 102 phys_addr_t base; 103 struct msm_clk_data *data; 104 }; 105 106 int qcom_cc_bind(struct udevice *parent); 107 void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0); 108 void clk_bcr_update(phys_addr_t apps_cmd_rgcr); 109 void clk_enable_cbc(phys_addr_t cbcr); 110 void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk); 111 const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate); 112 void clk_rcg_set_rate_mnd(phys_addr_t base, uint32_t cmd_rcgr, 113 int div, int m, int n, int source, u8 mnd_width); 114 void clk_rcg_set_rate(phys_addr_t base, uint32_t cmd_rcgr, int div, 115 int source); 116 void clk_phy_mux_enable(phys_addr_t base, uint32_t cmd_rcgr, bool enabled); 117 118 int qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id); 119 120 #endif 121