1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * OMAP clock controller support
4 *
5 * Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
6 */
7
8 #include <dm.h>
9 #include <dm/device_compat.h>
10 #include <clk-uclass.h>
11 #include <asm/arch-am33xx/clock.h>
12
13 struct clk_ti_ctrl_offs {
14 fdt_addr_t start;
15 fdt_size_t end;
16 };
17
18 struct clk_ti_ctrl_priv {
19 int offs_num;
20 struct clk_ti_ctrl_offs *offs;
21 };
22
clk_ti_ctrl_check_offs(struct clk * clk,fdt_addr_t offs)23 static int clk_ti_ctrl_check_offs(struct clk *clk, fdt_addr_t offs)
24 {
25 struct clk_ti_ctrl_priv *priv = dev_get_priv(clk->dev);
26 int i;
27
28 for (i = 0; i < priv->offs_num; i++) {
29 if (offs >= priv->offs[i].start && offs <= priv->offs[i].end)
30 return 0;
31 }
32
33 return -EFAULT;
34 }
35
clk_ti_ctrl_disable(struct clk * clk)36 static int clk_ti_ctrl_disable(struct clk *clk)
37 {
38 struct clk_ti_ctrl_priv *priv = dev_get_priv(clk->dev);
39 u32 *clk_modules[2] = { };
40 fdt_addr_t offs;
41 int err;
42
43 offs = priv->offs[0].start + clk->id;
44 err = clk_ti_ctrl_check_offs(clk, offs);
45 if (err) {
46 dev_err(clk->dev, "invalid offset: 0x%llx\n", (fdt64_t)offs);
47 return err;
48 }
49
50 clk_modules[0] = (u32 *)(offs);
51 dev_dbg(clk->dev, "disable module @ %p\n", clk_modules[0]);
52 do_disable_clocks(NULL, clk_modules, 1);
53 return 0;
54 }
55
clk_ti_ctrl_enable(struct clk * clk)56 static int clk_ti_ctrl_enable(struct clk *clk)
57 {
58 struct clk_ti_ctrl_priv *priv = dev_get_priv(clk->dev);
59 u32 *clk_modules[2] = { };
60 fdt_addr_t offs;
61 int err;
62
63 offs = priv->offs[0].start + clk->id;
64 err = clk_ti_ctrl_check_offs(clk, offs);
65 if (err) {
66 dev_err(clk->dev, "invalid offset: 0x%llx\n", (fdt64_t)offs);
67 return err;
68 }
69
70 clk_modules[0] = (u32 *)(offs);
71 dev_dbg(clk->dev, "enable module @ %p\n", clk_modules[0]);
72 do_enable_clocks(NULL, clk_modules, 1);
73 return 0;
74 }
75
clk_ti_ctrl_get_rate(struct clk * clk)76 static ulong clk_ti_ctrl_get_rate(struct clk *clk)
77 {
78 return 0;
79 }
80
clk_ti_ctrl_of_xlate(struct clk * clk,struct ofnode_phandle_args * args)81 static int clk_ti_ctrl_of_xlate(struct clk *clk,
82 struct ofnode_phandle_args *args)
83 {
84 if (args->args_count != 2) {
85 dev_err(clk->dev, "invalid args_count: %d\n", args->args_count);
86 return -EINVAL;
87 }
88
89 if (args->args_count)
90 clk->id = args->args[0];
91 else
92 clk->id = 0;
93
94 dev_dbg(clk->dev, "name=%s, id=%ld\n", clk->dev->name, clk->id);
95 return 0;
96 }
97
clk_ti_ctrl_of_to_plat(struct udevice * dev)98 static int clk_ti_ctrl_of_to_plat(struct udevice *dev)
99 {
100 struct clk_ti_ctrl_priv *priv = dev_get_priv(dev);
101 fdt_size_t fdt_size;
102 int i, size;
103
104 size = dev_read_size(dev, "reg");
105 if (size < 0) {
106 dev_err(dev, "failed to get 'reg' size\n");
107 return size;
108 }
109
110 priv->offs_num = size / 2 / sizeof(u32);
111 dev_dbg(dev, "size=%d, regs_num=%d\n", size, priv->offs_num);
112
113 priv->offs = kmalloc_array(priv->offs_num, sizeof(*priv->offs),
114 GFP_KERNEL);
115 if (!priv->offs)
116 return -ENOMEM;
117
118 for (i = 0; i < priv->offs_num; i++) {
119 priv->offs[i].start =
120 dev_read_addr_size_index(dev, i, &fdt_size);
121 if (priv->offs[i].start == FDT_ADDR_T_NONE) {
122 dev_err(dev, "failed to get offset %d\n", i);
123 return -EINVAL;
124 }
125
126 priv->offs[i].end = priv->offs[i].start + fdt_size;
127 dev_dbg(dev, "start=0x%016llx, end=0x%016llx\n",
128 (fdt64_t)priv->offs[i].start,
129 (fdt64_t)priv->offs[i].end);
130 }
131
132 return 0;
133 }
134
135 static struct clk_ops clk_ti_ctrl_ops = {
136 .of_xlate = clk_ti_ctrl_of_xlate,
137 .enable = clk_ti_ctrl_enable,
138 .disable = clk_ti_ctrl_disable,
139 .get_rate = clk_ti_ctrl_get_rate,
140 };
141
142 static const struct udevice_id clk_ti_ctrl_ids[] = {
143 {.compatible = "ti,clkctrl"},
144 {},
145 };
146
147 U_BOOT_DRIVER(clk_ti_ctrl) = {
148 .name = "ti_ctrl_clk",
149 .id = UCLASS_CLK,
150 .of_match = clk_ti_ctrl_ids,
151 .of_to_plat = clk_ti_ctrl_of_to_plat,
152 .ops = &clk_ti_ctrl_ops,
153 .priv_auto = sizeof(struct clk_ti_ctrl_priv),
154 };
155