1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2024 9elements GmbH
4 */
5
6 #include <cpu.h>
7 #include <cpu_func.h>
8 #include <dm.h>
9 #include <fdt_support.h>
10 #include <acpi/acpigen.h>
11 #include <asm/armv8/cpu.h>
12 #include <asm/cache.h>
13 #include <asm/io.h>
14 #include <asm/global_data.h>
15 #include <asm/system.h>
16 #include <asm-generic/sections.h>
17 #include <linux/bitops.h>
18 #include <linux/clk-provider.h>
19 #include <linux/delay.h>
20 #include "armv8_cpu.h"
21
22 DECLARE_GLOBAL_DATA_PTR;
23
24 struct bcm_plat {
25 u64 release_addr;
26 };
27
cpu_bcm_get_desc(const struct udevice * dev,char * buf,int size)28 static int cpu_bcm_get_desc(const struct udevice *dev, char *buf, int size)
29 {
30 struct cpu_plat *plat = dev_get_parent_plat(dev);
31 const char *name;
32
33 if (size < 32)
34 return -ENOSPC;
35
36 if (device_is_compatible(dev, "arm,cortex-a53"))
37 name = "A53";
38 else if (device_is_compatible(dev, "arm,cortex-a72"))
39 name = "A72";
40 else
41 name = "?";
42
43 snprintf(buf, size, "Broadcom Cortex-%s at %u MHz\n",
44 name, plat->timebase_freq);
45
46 return 0;
47 }
48
cpu_bcm_get_info(const struct udevice * dev,struct cpu_info * info)49 static int cpu_bcm_get_info(const struct udevice *dev, struct cpu_info *info)
50 {
51 struct cpu_plat *plat = dev_get_parent_plat(dev);
52
53 info->cpu_freq = plat->timebase_freq * 1000;
54 info->features = BIT(CPU_FEAT_L1_CACHE) | BIT(CPU_FEAT_MMU);
55
56 return 0;
57 }
58
cpu_bcm_get_count(const struct udevice * dev)59 static int cpu_bcm_get_count(const struct udevice *dev)
60 {
61 return uclass_id_count(UCLASS_CPU);
62 }
63
cpu_bcm_get_vendor(const struct udevice * dev,char * buf,int size)64 static int cpu_bcm_get_vendor(const struct udevice *dev, char *buf, int size)
65 {
66 snprintf(buf, size, "Broadcom");
67
68 return 0;
69 }
70
cpu_bcm_is_current(struct udevice * dev)71 static int cpu_bcm_is_current(struct udevice *dev)
72 {
73 struct cpu_plat *plat = dev_get_parent_plat(dev);
74
75 if (plat->cpu_id == (read_mpidr() & 0xffff))
76 return 1;
77
78 return 0;
79 }
80
81 /**
82 * bcm_cpu_on - Releases the secondary CPU from it's spintable
83 *
84 * Write the CPU's spintable mailbox and let the CPU enter U-Boot.
85 *
86 * @dev: Device to start
87 * @return: zero on success or error code on failure.
88 */
bcm_cpu_on(struct udevice * dev)89 static int bcm_cpu_on(struct udevice *dev)
90 {
91 struct bcm_plat *plat = dev_get_plat(dev);
92 ulong *start_address;
93
94 if (plat->release_addr == ~0ULL)
95 return -ENODATA;
96
97 start_address = map_physmem(plat->release_addr, sizeof(uintptr_t), MAP_NOCACHE);
98
99 /* Point secondary CPU to U-Boot entry */
100 *start_address = (uintptr_t)_start;
101
102 /* Make sure the other CPUs see the written start address */
103 if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
104 flush_dcache_all();
105
106 /* Send an event to wake up the secondary CPU. */
107 asm("dsb ishst\n"
108 "sev");
109
110 unmap_physmem(start_address, MAP_NOCACHE);
111
112 return 0;
113 }
114
115 static const struct cpu_ops cpu_bcm_ops = {
116 .get_desc = cpu_bcm_get_desc,
117 .get_info = cpu_bcm_get_info,
118 .get_count = cpu_bcm_get_count,
119 .get_vendor = cpu_bcm_get_vendor,
120 .is_current = cpu_bcm_is_current,
121 };
122
123 static const struct udevice_id cpu_bcm_ids[] = {
124 { .compatible = "arm,cortex-a53" }, /* RPi 3 */
125 { .compatible = "arm,cortex-a72" }, /* RPi 4 */
126 { }
127 };
128
bcm_cpu_bind(struct udevice * dev)129 static int bcm_cpu_bind(struct udevice *dev)
130 {
131 struct cpu_plat *plat = dev_get_parent_plat(dev);
132
133 plat->cpu_id = dev_read_addr(dev);
134
135 return 0;
136 }
137
138 /**
139 * bcm_cpu_of_to_plat - Gather spin-table release address
140 *
141 * Read the spin-table release address to allow all seconary CPUs to enter
142 * U-Boot when necessary.
143 *
144 * @dev: Device to start
145 */
bcm_cpu_of_to_plat(struct udevice * dev)146 static int bcm_cpu_of_to_plat(struct udevice *dev)
147 {
148 struct bcm_plat *plat = dev_get_plat(dev);
149 const char *prop;
150
151 if (CONFIG_IS_ENABLED(ARMV8_MULTIENTRY)) {
152 plat->release_addr = ~0ULL;
153
154 prop = dev_read_string(dev, "enable-method");
155 if (!prop || strcmp(prop, "spin-table"))
156 return -ENODEV;
157
158 plat->release_addr = dev_read_u64_default(dev, "cpu-release-addr", ~0ULL);
159
160 if (plat->release_addr == ~0ULL)
161 return -ENODEV;
162 }
163
164 return 0;
165 }
166
bcm_cpu_probe(struct udevice * dev)167 static int bcm_cpu_probe(struct udevice *dev)
168 {
169 struct cpu_plat *plat = dev_get_parent_plat(dev);
170 struct clk clk;
171 int ret;
172
173 /* Get a clock if it exists */
174 ret = clk_get_by_index(dev, 0, &clk);
175 if (!ret) {
176 ret = clk_enable(&clk);
177 if (ret && (ret != -ENOSYS || ret != -EOPNOTSUPP))
178 return ret;
179 ret = clk_get_rate(&clk);
180 if (IS_ERR_VALUE(ret))
181 return ret;
182 plat->timebase_freq = ret;
183 }
184
185 /*
186 * The armstub holds the secondary CPUs in a spinloop. When
187 * ARMV8_MULTIENTRY is enabled release the secondary CPUs and
188 * let them enter U-Boot as well.
189 */
190 if (CONFIG_IS_ENABLED(ARMV8_MULTIENTRY)) {
191 ret = bcm_cpu_on(dev);
192 if (ret)
193 return ret;
194 }
195
196 return ret;
197 }
198
199 struct acpi_ops bcm283x_cpu_acpi_ops = {
200 .fill_ssdt = armv8_cpu_fill_ssdt,
201 .fill_madt = armv8_cpu_fill_madt,
202 };
203
204 U_BOOT_DRIVER(cpu_bcm_drv) = {
205 .name = "bcm283x_cpu",
206 .id = UCLASS_CPU,
207 .of_match = cpu_bcm_ids,
208 .ops = &cpu_bcm_ops,
209 .probe = bcm_cpu_probe,
210 .bind = bcm_cpu_bind,
211 .of_to_plat = bcm_cpu_of_to_plat,
212 .plat_auto = sizeof(struct bcm_plat),
213 ACPI_OPS_PTR(&bcm283x_cpu_acpi_ops)
214 };
215