1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
4 * Copyright (C) 2020, Sean Anderson <seanga2@gmail.com>
5 */
6
7 #include <clk.h>
8 #include <cpu.h>
9 #include <dm.h>
10 #include <errno.h>
11 #include <log.h>
12 #include <asm/global_data.h>
13 #include <asm/sbi.h>
14 #include <dm/device-internal.h>
15 #include <dm/lists.h>
16 #include <linux/bitops.h>
17 #include <linux/err.h>
18
19 DECLARE_GLOBAL_DATA_PTR;
20
riscv_cpu_get_desc(const struct udevice * dev,char * buf,int size)21 static int riscv_cpu_get_desc(const struct udevice *dev, char *buf, int size)
22 {
23 const char *cpu;
24
25 cpu = dev_read_string(dev, "compatible");
26 if (!cpu || size < (strlen(cpu) + 1))
27 return -ENOSPC;
28
29 strcpy(buf, cpu);
30
31 return 0;
32 }
33
riscv_cpu_get_info(const struct udevice * dev,struct cpu_info * info)34 static int riscv_cpu_get_info(const struct udevice *dev, struct cpu_info *info)
35 {
36 int ret;
37 struct clk clk;
38 const char *mmu;
39 u32 i_cache_size;
40 u32 d_cache_size;
41
42 /* First try getting the frequency from the assigned clock */
43 ret = clk_get_by_index((struct udevice *)dev, 0, &clk);
44 if (!ret) {
45 ret = clk_get_rate(&clk);
46 if (!IS_ERR_VALUE(ret))
47 info->cpu_freq = ret;
48 }
49
50 if (!info->cpu_freq)
51 dev_read_u32(dev, "clock-frequency", (u32 *)&info->cpu_freq);
52
53 mmu = dev_read_string(dev, "mmu-type");
54 if (mmu)
55 info->features |= BIT(CPU_FEAT_MMU);
56
57 /* check if I cache is present */
58 ret = dev_read_u32(dev, "i-cache-size", &i_cache_size);
59 if (ret)
60 /* if not found check if d-cache is present */
61 ret = dev_read_u32(dev, "d-cache-size", &d_cache_size);
62
63 /* if either I or D cache is present set L1 cache feature */
64 if (!ret)
65 info->features |= BIT(CPU_FEAT_L1_CACHE);
66
67 return 0;
68 }
69
riscv_cpu_get_count(const struct udevice * dev)70 static int riscv_cpu_get_count(const struct udevice *dev)
71 {
72 ofnode node;
73 int num = 0;
74
75 ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
76 const char *device_type;
77
78 /* skip if hart is marked as not available in the device tree */
79 if (!ofnode_is_enabled(node))
80 continue;
81
82 device_type = ofnode_read_string(node, "device_type");
83 if (!device_type)
84 continue;
85 if (strcmp(device_type, "cpu") == 0)
86 num++;
87 }
88
89 return num;
90 }
91
riscv_cpu_bind(struct udevice * dev)92 static int riscv_cpu_bind(struct udevice *dev)
93 {
94 struct cpu_plat *plat = dev_get_parent_plat(dev);
95 struct driver *drv;
96 int ret;
97 long mvendorid;
98
99 /* save the hart id */
100 plat->cpu_id = dev_read_addr(dev);
101 /* provide data for SMBIOS */
102 if (IS_ENABLED(CONFIG_64BIT))
103 plat->family = 0x201;
104 else
105 plat->family = 0x200;
106 if (CONFIG_IS_ENABLED(RISCV_SMODE)) {
107 /*
108 * For RISC-V CPUs the SMBIOS Processor ID field contains
109 * the Machine Vendor ID from CSR mvendorid.
110 */
111 ret = sbi_get_mvendorid(&mvendorid);
112 if (!ret)
113 plat->id[0] = mvendorid;
114 }
115 /* first examine the property in current cpu node */
116 ret = dev_read_u32(dev, "timebase-frequency", &plat->timebase_freq);
117 /* if not found, then look at the parent /cpus node */
118 if (ret)
119 dev_read_u32(dev->parent, "timebase-frequency",
120 &plat->timebase_freq);
121
122 /*
123 * Bind riscv-timer driver on boot hart.
124 *
125 * We only instantiate one timer device which is enough for U-Boot.
126 * Pass the "timebase-frequency" value as the driver data for the
127 * timer device.
128 *
129 * Return value is not checked since it's possible that the timer
130 * driver is not included.
131 */
132 if (plat->cpu_id == gd->arch.boot_hart && plat->timebase_freq) {
133 drv = lists_driver_lookup_name("riscv_timer");
134 if (!drv) {
135 debug("Cannot find the timer driver, not included?\n");
136 return 0;
137 }
138
139 device_bind_with_driver_data(dev, drv, "riscv_timer",
140 plat->timebase_freq, ofnode_null(),
141 NULL);
142 }
143
144 return 0;
145 }
146
riscv_cpu_probe(struct udevice * dev)147 static int riscv_cpu_probe(struct udevice *dev)
148 {
149 int ret = 0;
150 struct clk clk;
151
152 /* Get a clock if it exists */
153 ret = clk_get_by_index(dev, 0, &clk);
154 if (ret)
155 return 0;
156
157 ret = clk_enable(&clk);
158 if (ret == -ENOSYS || ret == -ENOTSUPP)
159 return 0;
160 else
161 return ret;
162 }
163
164 static const struct cpu_ops riscv_cpu_ops = {
165 .get_desc = riscv_cpu_get_desc,
166 .get_info = riscv_cpu_get_info,
167 .get_count = riscv_cpu_get_count,
168 };
169
170 static const struct udevice_id riscv_cpu_ids[] = {
171 { .compatible = "riscv" },
172 { }
173 };
174
175 U_BOOT_DRIVER(riscv_cpu) = {
176 .name = "riscv_cpu",
177 .id = UCLASS_CPU,
178 .of_match = riscv_cpu_ids,
179 .bind = riscv_cpu_bind,
180 .probe = riscv_cpu_probe,
181 .ops = &riscv_cpu_ops,
182 .flags = DM_FLAG_PRE_RELOC,
183 };
184