1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /*
3  * Copyright Altera Corporation (C) 2012-2015
4  */
5 
6 #ifndef _SEQUENCER_H_
7 #define _SEQUENCER_H_
8 
9 #include <config.h>
10 
11 #define RW_MGR_NUM_DM_PER_WRITE_GROUP (seq->rwcfg->mem_data_mask_width \
12 	/ seq->rwcfg->mem_if_write_dqs_width)
13 #define RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP ( \
14 	seq->rwcfg->true_mem_data_mask_width \
15 	/ seq->rwcfg->mem_if_write_dqs_width)
16 
17 #define RW_MGR_NUM_DQS_PER_WRITE_GROUP (seq->rwcfg->mem_if_read_dqs_width \
18 	/ seq->rwcfg->mem_if_write_dqs_width)
19 #define NUM_RANKS_PER_SHADOW_REG (seq->rwcfg->mem_number_of_ranks \
20 	/ NUM_SHADOW_REGS)
21 
22 #define RW_MGR_RUN_SINGLE_GROUP_OFFSET		0x0
23 #define RW_MGR_RUN_ALL_GROUPS_OFFSET		0x0400
24 #define RW_MGR_RESET_READ_DATAPATH_OFFSET	0x1000
25 #define RW_MGR_SET_CS_AND_ODT_MASK_OFFSET	0x1400
26 #define RW_MGR_INST_ROM_WRITE_OFFSET		0x1800
27 #define RW_MGR_AC_ROM_WRITE_OFFSET		0x1C00
28 
29 #define NUM_SHADOW_REGS			1
30 
31 #define RW_MGR_RANK_NONE		0xFF
32 #define RW_MGR_RANK_ALL			0x00
33 
34 #define RW_MGR_ODT_MODE_OFF		0
35 #define RW_MGR_ODT_MODE_READ_WRITE	1
36 
37 #define NUM_CALIB_REPEAT		1
38 
39 #define NUM_READ_TESTS			7
40 #define NUM_READ_PB_TESTS		7
41 #define NUM_WRITE_TESTS			15
42 #define NUM_WRITE_PB_TESTS		31
43 
44 #define PASS_ALL_BITS			1
45 #define PASS_ONE_BIT			0
46 
47 /* calibration stages */
48 #define CAL_STAGE_NIL			0
49 #define CAL_STAGE_VFIFO			1
50 #define CAL_STAGE_WLEVEL		2
51 #define CAL_STAGE_LFIFO			3
52 #define CAL_STAGE_WRITES		4
53 #define CAL_STAGE_FULLTEST		5
54 #define CAL_STAGE_REFRESH		6
55 #define CAL_STAGE_CAL_SKIPPED		7
56 #define CAL_STAGE_CAL_ABORTED		8
57 #define CAL_STAGE_VFIFO_AFTER_WRITES	9
58 
59 /* calibration substages */
60 #define CAL_SUBSTAGE_NIL		0
61 #define CAL_SUBSTAGE_GUARANTEED_READ	1
62 #define CAL_SUBSTAGE_DQS_EN_PHASE	2
63 #define CAL_SUBSTAGE_VFIFO_CENTER	3
64 #define CAL_SUBSTAGE_WORKING_DELAY	1
65 #define CAL_SUBSTAGE_LAST_WORKING_DELAY	2
66 #define CAL_SUBSTAGE_WLEVEL_COPY	3
67 #define CAL_SUBSTAGE_WRITES_CENTER	1
68 #define CAL_SUBSTAGE_READ_LATENCY	1
69 #define CAL_SUBSTAGE_REFRESH		1
70 
71 #define SCC_MGR_GROUP_COUNTER_OFFSET		0x0000
72 #define SCC_MGR_DQS_IN_DELAY_OFFSET		0x0100
73 #define SCC_MGR_DQS_EN_PHASE_OFFSET		0x0200
74 #define SCC_MGR_DQS_EN_DELAY_OFFSET		0x0300
75 #define SCC_MGR_DQDQS_OUT_PHASE_OFFSET		0x0400
76 #define SCC_MGR_OCT_OUT1_DELAY_OFFSET		0x0500
77 #define SCC_MGR_IO_OUT1_DELAY_OFFSET		0x0700
78 #define SCC_MGR_IO_IN_DELAY_OFFSET		0x0900
79 
80 /* HHP-HPS-specific versions of some commands */
81 #define SCC_MGR_DQS_EN_DELAY_GATE_OFFSET	0x0600
82 #define SCC_MGR_IO_OE_DELAY_OFFSET		0x0800
83 #define SCC_MGR_HHP_GLOBALS_OFFSET		0x0A00
84 #define SCC_MGR_HHP_RFILE_OFFSET		0x0B00
85 #define SCC_MGR_AFI_CAL_INIT_OFFSET		0x0D00
86 
87 #define SDR_PHYGRP_SCCGRP_ADDRESS		(SOCFPGA_SDR_ADDRESS | 0x0)
88 #define SDR_PHYGRP_PHYMGRGRP_ADDRESS		(SOCFPGA_SDR_ADDRESS | 0x1000)
89 #define SDR_PHYGRP_RWMGRGRP_ADDRESS		(SOCFPGA_SDR_ADDRESS | 0x2000)
90 #define SDR_PHYGRP_DATAMGRGRP_ADDRESS		(SOCFPGA_SDR_ADDRESS | 0x4000)
91 #define SDR_PHYGRP_REGFILEGRP_ADDRESS		(SOCFPGA_SDR_ADDRESS | 0x4800)
92 
93 #define PHY_MGR_CAL_RESET		(0)
94 #define PHY_MGR_CAL_SUCCESS		(1)
95 #define PHY_MGR_CAL_FAIL		(2)
96 
97 #define CALIB_SKIP_DELAY_LOOPS		(1 << 0)
98 #define CALIB_SKIP_ALL_BITS_CHK		(1 << 1)
99 #define CALIB_SKIP_DELAY_SWEEPS		(1 << 2)
100 #define CALIB_SKIP_VFIFO		(1 << 3)
101 #define CALIB_SKIP_LFIFO		(1 << 4)
102 #define CALIB_SKIP_WLEVEL		(1 << 5)
103 #define CALIB_SKIP_WRITES		(1 << 6)
104 #define CALIB_SKIP_FULL_TEST		(1 << 7)
105 #define CALIB_SKIP_ALL			(CALIB_SKIP_VFIFO | \
106 				CALIB_SKIP_LFIFO | CALIB_SKIP_WLEVEL | \
107 				CALIB_SKIP_WRITES | CALIB_SKIP_FULL_TEST)
108 #define CALIB_IN_RTL_SIM			(1 << 8)
109 
110 /* Scan chain manager command addresses */
111 #define READ_SCC_OCT_OUT2_DELAY			0
112 #define READ_SCC_DQ_OUT2_DELAY			0
113 #define READ_SCC_DQS_IO_OUT2_DELAY		0
114 #define READ_SCC_DM_IO_OUT2_DELAY		0
115 
116 /* HHP-HPS-specific values */
117 #define SCC_MGR_HHP_EXTRAS_OFFSET			0
118 #define SCC_MGR_HHP_DQSE_MAP_OFFSET			1
119 
120 /* PHY Debug mode flag constants */
121 #define PHY_DEBUG_IN_DEBUG_MODE 0x00000001
122 #define PHY_DEBUG_ENABLE_CAL_RPT 0x00000002
123 #define PHY_DEBUG_ENABLE_MARGIN_RPT 0x00000004
124 #define PHY_DEBUG_SWEEP_ALL_GROUPS 0x00000008
125 #define PHY_DEBUG_DISABLE_GUARANTEED_READ 0x00000010
126 #define PHY_DEBUG_ENABLE_NON_DESTRUCTIVE_CALIBRATION 0x00000020
127 
128 struct socfpga_sdr_rw_load_manager {
129 	u32	load_cntr0;
130 	u32	load_cntr1;
131 	u32	load_cntr2;
132 	u32	load_cntr3;
133 };
134 
135 struct socfpga_sdr_rw_load_jump_manager {
136 	u32	load_jump_add0;
137 	u32	load_jump_add1;
138 	u32	load_jump_add2;
139 	u32	load_jump_add3;
140 };
141 
142 struct socfpga_sdr_reg_file {
143 	u32 signature;
144 	u32 debug_data_addr;
145 	u32 cur_stage;
146 	u32 fom;
147 	u32 failing_stage;
148 	u32 debug1;
149 	u32 debug2;
150 	u32 dtaps_per_ptap;
151 	u32 trk_sample_count;
152 	u32 trk_longidle;
153 	u32 delays;
154 	u32 trk_rw_mgr_addr;
155 	u32 trk_read_dqs_width;
156 	u32 trk_rfsh;
157 };
158 
159 /* parameter variable holder */
160 struct param_type {
161 	u32	read_correct_mask;
162 	u32	read_correct_mask_vg;
163 	u32	write_correct_mask;
164 	u32	write_correct_mask_vg;
165 };
166 
167 /* global variable holder */
168 struct gbl_type {
169 	uint32_t phy_debug_mode_flags;
170 
171 	/* current read latency */
172 
173 	uint32_t curr_read_lat;
174 
175 	/* error code */
176 
177 	uint32_t error_substage;
178 	uint32_t error_stage;
179 	uint32_t error_group;
180 
181 	/* figure-of-merit in, figure-of-merit out */
182 
183 	uint32_t fom_in;
184 	uint32_t fom_out;
185 
186 	/*USER Number of RW Mgr NOP cycles between
187 	write command and write data */
188 	uint32_t rw_wl_nop_cycles;
189 };
190 
191 struct socfpga_sdr_scc_mgr {
192 	u32	dqs_ena;
193 	u32	dqs_io_ena;
194 	u32	dq_ena;
195 	u32	dm_ena;
196 	u32	__padding1[4];
197 	u32	update;
198 	u32	__padding2[7];
199 	u32	active_rank;
200 };
201 
202 /* PHY manager configuration registers. */
203 struct socfpga_phy_mgr_cfg {
204 	u32	phy_rlat;
205 	u32	reset_mem_stbl;
206 	u32	mux_sel;
207 	u32	cal_status;
208 	u32	cal_debug_info;
209 	u32	vfifo_rd_en_ovrd;
210 	u32	afi_wlat;
211 	u32	afi_rlat;
212 };
213 
214 /* PHY manager command addresses. */
215 struct socfpga_phy_mgr_cmd {
216 	u32	inc_vfifo_fr;
217 	u32	inc_vfifo_hard_phy;
218 	u32	fifo_reset;
219 	u32	inc_vfifo_fr_hr;
220 	u32	inc_vfifo_qr;
221 };
222 
223 struct socfpga_data_mgr {
224 	u32	__padding1;
225 	u32	t_wl_add;
226 	u32	mem_t_add;
227 	u32	t_rl_add;
228 };
229 
230 /* This struct describes the controller @ SOCFPGA_SDR_ADDRESS */
231 struct socfpga_sdr {
232 	/* SDR_PHYGRP_SCCGRP_ADDRESS */
233 	u8 _align1[0xe00];
234 	/* SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00 */
235 	struct socfpga_sdr_scc_mgr sdr_scc_mgr;
236 	u8 _align2[0x1bc];
237 	/* SDR_PHYGRP_PHYMGRGRP_ADDRESS */
238 	struct socfpga_phy_mgr_cmd phy_mgr_cmd;
239 	u8 _align3[0x2c];
240 	/* SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40 */
241 	struct socfpga_phy_mgr_cfg phy_mgr_cfg;
242 	u8 _align4[0xfa0];
243 	/* SDR_PHYGRP_RWMGRGRP_ADDRESS */
244 	u8 rwmgr_grp[0x800];
245 	/* SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800 */
246 	struct socfpga_sdr_rw_load_manager sdr_rw_load_mgr_regs;
247 	u8 _align5[0x3f0];
248 	/* SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00 */
249 	struct socfpga_sdr_rw_load_jump_manager sdr_rw_load_jump_mgr_regs;
250 	u8 _align6[0x13f0];
251 	/* SDR_PHYGRP_DATAMGRGRP_ADDRESS */
252 	struct socfpga_data_mgr data_mgr;
253 	u8 _align7[0x7f0];
254 	/* SDR_PHYGRP_REGFILEGRP_ADDRESS */
255 	struct socfpga_sdr_reg_file sdr_reg_file;
256 	u8 _align8[0x7c8];
257 	/* SDR_CTRLGRP_ADDRESS */
258 	struct socfpga_sdr_ctrl sdr_ctrl;
259 	u8 _align9[0xea4];
260 };
261 
262 struct socfpga_sdrseq {
263 	const struct socfpga_sdram_rw_mgr_config *rwcfg;
264 	const struct socfpga_sdram_io_config *iocfg;
265 	const struct socfpga_sdram_misc_config *misccfg;
266 	/* calibration steps requested by the rtl */
267 	u16 dyn_calib_steps;
268 	/*
269 	 * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
270 	 * instead of static, we use boolean logic to select between
271 	 * non-skip and skip values
272 	 *
273 	 * The mask is set to include all bits when not-skipping, but is
274 	 * zero when skipping
275 	 */
276 
277 	u16 skip_delay_mask;	/* mask off bits when skipping/not-skipping */
278 	struct gbl_type gbl;
279 	struct param_type param;
280 };
281 
282 int sdram_calibration_full(struct socfpga_sdr *sdr);
283 bool dram_is_ddr(const u8 ddr);
284 
285 #endif /* _SEQUENCER_H_ */
286