1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright 2008-2014 Freescale Semiconductor, Inc.
4 * Copyright 2021 NXP
5 */
6
7 /*
8 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
9 * Based on code from spd_sdram.c
10 * Author: James Yang [at freescale.com]
11 */
12
13 #include <config.h>
14 #include <display_options.h>
15 #include <dm.h>
16 #include <i2c.h>
17 #include <fsl_ddr_sdram.h>
18 #include <fsl_ddr.h>
19 #include <init.h>
20 #include <log.h>
21 #include <asm/bitops.h>
22
23 /*
24 * CFG_SYS_FSL_DDR_SDRAM_BASE_PHY is the physical address from the view
25 * of DDR controllers. It is the same as CFG_SYS_DDR_SDRAM_BASE for
26 * all Power SoCs. But it could be different for ARM SoCs. For example,
27 * fsl_lsch3 has a mapping mechanism to map DDR memory to ranges (in order) of
28 * 0x00_8000_0000 ~ 0x00_ffff_ffff
29 * 0x80_8000_0000 ~ 0xff_ffff_ffff
30 */
31 #ifndef CFG_SYS_FSL_DDR_SDRAM_BASE_PHY
32 #ifdef CONFIG_MPC83xx
33 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CFG_SYS_SDRAM_BASE
34 #else
35 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CFG_SYS_DDR_SDRAM_BASE
36 #endif
37 #endif
38
39 #ifdef CONFIG_PPC
40 #include <asm/fsl_law.h>
41
42 void fsl_ddr_set_lawbar(
43 const common_timing_params_t *memctl_common_params,
44 unsigned int memctl_interleaved,
45 unsigned int ctrl_num);
46 #endif
47
48 void fsl_ddr_set_intl3r(const unsigned int granule_size);
49 #if defined(SPD_EEPROM_ADDRESS) || \
50 defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \
51 defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4)
52 #if (CONFIG_SYS_NUM_DDR_CTLRS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
53 u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
54 [0][0] = SPD_EEPROM_ADDRESS,
55 };
56 #elif (CONFIG_SYS_NUM_DDR_CTLRS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
57 u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
58 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
59 [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
60 };
61 #elif (CONFIG_SYS_NUM_DDR_CTLRS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
62 u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
63 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
64 [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */
65 };
66 #elif (CONFIG_SYS_NUM_DDR_CTLRS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
67 u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
68 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
69 [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
70 [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */
71 [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */
72 };
73 #elif (CONFIG_SYS_NUM_DDR_CTLRS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
74 u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
75 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
76 [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */
77 [2][0] = SPD_EEPROM_ADDRESS3, /* controller 3 */
78 };
79 #elif (CONFIG_SYS_NUM_DDR_CTLRS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
80 u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
81 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
82 [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
83 [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */
84 [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */
85 [2][0] = SPD_EEPROM_ADDRESS5, /* controller 3 */
86 [2][1] = SPD_EEPROM_ADDRESS6, /* controller 3 */
87 };
88
89 #endif
90
91 #if CONFIG_IS_ENABLED(DM_I2C)
92 #define DEV_TYPE struct udevice
93 #else
94 /* Local udevice */
95 struct ludevice {
96 u8 chip;
97 };
98
99 #define DEV_TYPE struct ludevice
100
101 #endif
102
103 #define SPD_SPA0_ADDRESS 0x36
104 #define SPD_SPA1_ADDRESS 0x37
105
ddr_i2c_read(DEV_TYPE * dev,unsigned int addr,int alen,uint8_t * buf,int len)106 static int ddr_i2c_read(DEV_TYPE *dev, unsigned int addr,
107 int alen, uint8_t *buf, int len)
108 {
109 int ret;
110
111 #if CONFIG_IS_ENABLED(DM_I2C)
112 ret = dm_i2c_read(dev, 0, buf, len);
113 #else
114 ret = 0;
115 #endif
116
117 return ret;
118 }
119
120 #ifdef CONFIG_SYS_FSL_DDR4
ddr_i2c_dummy_write(unsigned int chip_addr)121 static int ddr_i2c_dummy_write(unsigned int chip_addr)
122 {
123 uint8_t buf = 0;
124
125 #if CONFIG_IS_ENABLED(DM_I2C)
126 struct udevice *dev;
127 int ret;
128
129 ret = i2c_get_chip_for_busnum(CONFIG_SYS_SPD_BUS_NUM, chip_addr,
130 1, &dev);
131 if (ret) {
132 printf("%s: Cannot find udev for a bus %d\n", __func__,
133 CONFIG_SYS_SPD_BUS_NUM);
134 return ret;
135 }
136
137 return dm_i2c_write(dev, 0, &buf, 1);
138 #else
139 return i2c_write(chip_addr, 0, 1, &buf, 1);
140 #endif
141
142 return 0;
143 }
144 #endif
145
__get_spd(generic_spd_eeprom_t * spd,u8 i2c_address)146 static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
147 {
148 int ret;
149 DEV_TYPE *dev;
150
151 #if CONFIG_IS_ENABLED(DM_I2C)
152 ret = i2c_get_chip_for_busnum(CONFIG_SYS_SPD_BUS_NUM, i2c_address,
153 1, &dev);
154 if (ret) {
155 printf("%s: Cannot find udev for a bus %d\n", __func__,
156 CONFIG_SYS_SPD_BUS_NUM);
157 return;
158 }
159 #else /* Non DM I2C support - will be removed */
160 struct ludevice ldev = {
161 .chip = i2c_address,
162 };
163 dev = &ldev;
164
165 #endif
166
167 #ifdef CONFIG_SYS_FSL_DDR4
168 /*
169 * DDR4 SPD has 384 to 512 bytes
170 * To access the lower 256 bytes, we need to set EE page address to 0
171 * To access the upper 256 bytes, we need to set EE page address to 1
172 * See Jedec standar No. 21-C for detail
173 */
174 ddr_i2c_dummy_write(SPD_SPA0_ADDRESS);
175 ret = ddr_i2c_read(dev, 0, 1, (uchar *)spd, 256);
176 if (!ret) {
177 ddr_i2c_dummy_write(SPD_SPA1_ADDRESS);
178 ret = ddr_i2c_read(dev, 0, 1, (uchar *)((ulong)spd + 256),
179 min(256,
180 (int)sizeof(generic_spd_eeprom_t)
181 - 256));
182 }
183
184 #else
185 ret = ddr_i2c_read(dev, 0, 1, (uchar *)spd,
186 sizeof(generic_spd_eeprom_t));
187 #endif
188
189 if (ret) {
190 if (i2c_address ==
191 #ifdef SPD_EEPROM_ADDRESS
192 SPD_EEPROM_ADDRESS
193 #elif defined(SPD_EEPROM_ADDRESS1)
194 SPD_EEPROM_ADDRESS1
195 #endif
196 ) {
197 printf("DDR: failed to read SPD from address %u\n",
198 i2c_address);
199 } else {
200 debug("DDR: failed to read SPD from address %u\n",
201 i2c_address);
202 }
203 memset(spd, 0, sizeof(generic_spd_eeprom_t));
204 }
205 }
206
207 __attribute__((weak, alias("__get_spd")))
208 void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address);
209
210 /* This function allows boards to update SPD address */
update_spd_address(unsigned int ctrl_num,unsigned int slot,unsigned int * addr)211 __weak void update_spd_address(unsigned int ctrl_num,
212 unsigned int slot,
213 unsigned int *addr)
214 {
215 }
216
fsl_ddr_get_spd(generic_spd_eeprom_t * ctrl_dimms_spd,unsigned int ctrl_num,unsigned int dimm_slots_per_ctrl)217 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
218 unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl)
219 {
220 unsigned int i;
221 unsigned int i2c_address = 0;
222
223 if (ctrl_num >= CONFIG_SYS_NUM_DDR_CTLRS) {
224 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
225 return;
226 }
227
228 for (i = 0; i < dimm_slots_per_ctrl; i++) {
229 i2c_address = spd_i2c_addr[ctrl_num][i];
230 update_spd_address(ctrl_num, i, &i2c_address);
231 get_spd(&(ctrl_dimms_spd[i]), i2c_address);
232 }
233 }
234 #else
fsl_ddr_get_spd(generic_spd_eeprom_t * ctrl_dimms_spd,unsigned int ctrl_num,unsigned int dimm_slots_per_ctrl)235 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
236 unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl)
237 {
238 }
239 #endif /* SPD_EEPROM_ADDRESSx */
240
241 /*
242 * ASSUMPTIONS:
243 * - Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller
244 * - Same memory data bus width on all controllers
245 *
246 * NOTES:
247 *
248 * The memory controller and associated documentation use confusing
249 * terminology when referring to the orgranization of DRAM.
250 *
251 * Here is a terminology translation table:
252 *
253 * memory controller/documention |industry |this code |signals
254 * -------------------------------|-----------|-----------|-----------------
255 * physical bank/bank |rank |rank |chip select (CS)
256 * logical bank/sub-bank |bank |bank |bank address (BA)
257 * page/row |row |page |row address
258 * ??? |column |column |column address
259 *
260 * The naming confusion is further exacerbated by the descriptions of the
261 * memory controller interleaving feature, where accesses are interleaved
262 * _BETWEEN_ two seperate memory controllers. This is configured only in
263 * CS0_CONFIG[INTLV_CTL] of each memory controller.
264 *
265 * memory controller documentation | number of chip selects
266 * | per memory controller supported
267 * --------------------------------|-----------------------------------------
268 * cache line interleaving | 1 (CS0 only)
269 * page interleaving | 1 (CS0 only)
270 * bank interleaving | 1 (CS0 only)
271 * superbank interleraving | depends on bank (chip select)
272 * | interleraving [rank interleaving]
273 * | mode used on every memory controller
274 *
275 * Even further confusing is the existence of the interleaving feature
276 * _WITHIN_ each memory controller. The feature is referred to in
277 * documentation as chip select interleaving or bank interleaving,
278 * although it is configured in the DDR_SDRAM_CFG field.
279 *
280 * Name of field | documentation name | this code
281 * -----------------------------|-----------------------|------------------
282 * DDR_SDRAM_CFG[BA_INTLV_CTL] | Bank (chip select) | rank interleaving
283 * | interleaving
284 */
285
286 const char *step_string_tbl[] = {
287 "STEP_GET_SPD",
288 "STEP_COMPUTE_DIMM_PARMS",
289 "STEP_COMPUTE_COMMON_PARMS",
290 "STEP_GATHER_OPTS",
291 "STEP_ASSIGN_ADDRESSES",
292 "STEP_COMPUTE_REGS",
293 "STEP_PROGRAM_REGS",
294 "STEP_ALL"
295 };
296
step_to_string(unsigned int step)297 const char * step_to_string(unsigned int step) {
298
299 unsigned int s = __ilog2(step);
300
301 if (s <= 31) {
302 if ((1 << s) != step)
303 return step_string_tbl[7];
304 } else {
305 if ((1 << (s - 32)) != step)
306 return step_string_tbl[7];
307 }
308 if (s >= ARRAY_SIZE(step_string_tbl)) {
309 printf("Error for the step in %s\n", __func__);
310 s = 0;
311 }
312
313 return step_string_tbl[s];
314 }
315
__step_assign_addresses(fsl_ddr_info_t * pinfo,unsigned int dbw_cap_adj[])316 static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo,
317 unsigned int dbw_cap_adj[])
318 {
319 unsigned int i, j;
320 unsigned long long total_mem, current_mem_base, total_ctlr_mem;
321 unsigned long long rank_density, ctlr_density = 0;
322 unsigned int first_ctrl = pinfo->first_ctrl;
323 unsigned int last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
324
325 /*
326 * If a reduced data width is requested, but the SPD
327 * specifies a physically wider device, adjust the
328 * computed dimm capacities accordingly before
329 * assigning addresses.
330 */
331 for (i = first_ctrl; i <= last_ctrl; i++) {
332 unsigned int found = 0;
333
334 switch (pinfo->memctl_opts[i].data_bus_width) {
335 case 2:
336 /* 16-bit */
337 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
338 unsigned int dw;
339 if (!pinfo->dimm_params[i][j].n_ranks)
340 continue;
341 dw = pinfo->dimm_params[i][j].primary_sdram_width;
342 if ((dw == 72 || dw == 64)) {
343 dbw_cap_adj[i] = 2;
344 break;
345 } else if ((dw == 40 || dw == 32)) {
346 dbw_cap_adj[i] = 1;
347 break;
348 }
349 }
350 break;
351
352 case 1:
353 /* 32-bit */
354 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
355 unsigned int dw;
356 dw = pinfo->dimm_params[i][j].data_width;
357 if (pinfo->dimm_params[i][j].n_ranks
358 && (dw == 72 || dw == 64)) {
359 /*
360 * FIXME: can't really do it
361 * like this because this just
362 * further reduces the memory
363 */
364 found = 1;
365 break;
366 }
367 }
368 if (found) {
369 dbw_cap_adj[i] = 1;
370 }
371 break;
372
373 case 0:
374 /* 64-bit */
375 break;
376
377 default:
378 printf("unexpected data bus width "
379 "specified controller %u\n", i);
380 return 1;
381 }
382 debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]);
383 }
384
385 current_mem_base = pinfo->mem_base;
386 total_mem = 0;
387 if (pinfo->memctl_opts[first_ctrl].memctl_interleaving) {
388 rank_density = pinfo->dimm_params[first_ctrl][0].rank_density >>
389 dbw_cap_adj[first_ctrl];
390 switch (pinfo->memctl_opts[first_ctrl].ba_intlv_ctl &
391 FSL_DDR_CS0_CS1_CS2_CS3) {
392 case FSL_DDR_CS0_CS1_CS2_CS3:
393 ctlr_density = 4 * rank_density;
394 break;
395 case FSL_DDR_CS0_CS1:
396 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
397 ctlr_density = 2 * rank_density;
398 break;
399 case FSL_DDR_CS2_CS3:
400 default:
401 ctlr_density = rank_density;
402 break;
403 }
404 debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
405 rank_density, ctlr_density);
406 for (i = first_ctrl; i <= last_ctrl; i++) {
407 if (pinfo->memctl_opts[i].memctl_interleaving) {
408 switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
409 case FSL_DDR_256B_INTERLEAVING:
410 case FSL_DDR_CACHE_LINE_INTERLEAVING:
411 case FSL_DDR_PAGE_INTERLEAVING:
412 case FSL_DDR_BANK_INTERLEAVING:
413 case FSL_DDR_SUPERBANK_INTERLEAVING:
414 total_ctlr_mem = 2 * ctlr_density;
415 break;
416 case FSL_DDR_3WAY_1KB_INTERLEAVING:
417 case FSL_DDR_3WAY_4KB_INTERLEAVING:
418 case FSL_DDR_3WAY_8KB_INTERLEAVING:
419 total_ctlr_mem = 3 * ctlr_density;
420 break;
421 case FSL_DDR_4WAY_1KB_INTERLEAVING:
422 case FSL_DDR_4WAY_4KB_INTERLEAVING:
423 case FSL_DDR_4WAY_8KB_INTERLEAVING:
424 total_ctlr_mem = 4 * ctlr_density;
425 break;
426 default:
427 panic("Unknown interleaving mode");
428 }
429 pinfo->common_timing_params[i].base_address =
430 current_mem_base;
431 pinfo->common_timing_params[i].total_mem =
432 total_ctlr_mem;
433 total_mem = current_mem_base + total_ctlr_mem;
434 debug("ctrl %d base 0x%llx\n", i, current_mem_base);
435 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
436 } else {
437 /* when 3rd controller not interleaved */
438 current_mem_base = total_mem;
439 total_ctlr_mem = 0;
440 pinfo->common_timing_params[i].base_address =
441 current_mem_base;
442 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
443 unsigned long long cap =
444 pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
445 pinfo->dimm_params[i][j].base_address =
446 current_mem_base;
447 debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
448 current_mem_base += cap;
449 total_ctlr_mem += cap;
450 }
451 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
452 pinfo->common_timing_params[i].total_mem =
453 total_ctlr_mem;
454 total_mem += total_ctlr_mem;
455 }
456 }
457 } else {
458 /*
459 * Simple linear assignment if memory
460 * controllers are not interleaved.
461 */
462 for (i = first_ctrl; i <= last_ctrl; i++) {
463 total_ctlr_mem = 0;
464 pinfo->common_timing_params[i].base_address =
465 current_mem_base;
466 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
467 /* Compute DIMM base addresses. */
468 unsigned long long cap =
469 pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
470 pinfo->dimm_params[i][j].base_address =
471 current_mem_base;
472 debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
473 current_mem_base += cap;
474 total_ctlr_mem += cap;
475 }
476 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
477 pinfo->common_timing_params[i].total_mem =
478 total_ctlr_mem;
479 total_mem += total_ctlr_mem;
480 }
481 }
482 debug("Total mem by %s is 0x%llx\n", __func__, total_mem);
483
484 return total_mem;
485 }
486
487 /* Use weak function to allow board file to override the address assignment */
488 __attribute__((weak, alias("__step_assign_addresses")))
489 unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
490 unsigned int dbw_cap_adj[]);
491
492 unsigned long long
fsl_ddr_compute(fsl_ddr_info_t * pinfo,unsigned int start_step,unsigned int size_only)493 fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
494 unsigned int size_only)
495 {
496 unsigned int i, j;
497 unsigned long long total_mem = 0;
498 int assert_reset = 0;
499 unsigned int first_ctrl = pinfo->first_ctrl;
500 unsigned int last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
501 __maybe_unused int retval;
502 __maybe_unused bool goodspd = false;
503 __maybe_unused int dimm_slots_per_ctrl = pinfo->dimm_slots_per_ctrl;
504
505 fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg;
506 common_timing_params_t *timing_params = pinfo->common_timing_params;
507 if (pinfo->board_need_mem_reset)
508 assert_reset = pinfo->board_need_mem_reset();
509
510 /* data bus width capacity adjust shift amount */
511 unsigned int dbw_capacity_adjust[CONFIG_SYS_NUM_DDR_CTLRS];
512
513 for (i = first_ctrl; i <= last_ctrl; i++)
514 dbw_capacity_adjust[i] = 0;
515
516 debug("starting at step %u (%s)\n",
517 start_step, step_to_string(start_step));
518
519 switch (start_step) {
520 case STEP_GET_SPD:
521 #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
522 /* STEP 1: Gather all DIMM SPD data */
523 for (i = first_ctrl; i <= last_ctrl; i++) {
524 fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i,
525 dimm_slots_per_ctrl);
526 }
527
528 case STEP_COMPUTE_DIMM_PARMS:
529 /* STEP 2: Compute DIMM parameters from SPD data */
530
531 for (i = first_ctrl; i <= last_ctrl; i++) {
532 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
533 generic_spd_eeprom_t *spd =
534 &(pinfo->spd_installed_dimms[i][j]);
535 dimm_params_t *pdimm =
536 &(pinfo->dimm_params[i][j]);
537 retval = compute_dimm_parameters(
538 i, spd, pdimm, j);
539 #ifdef CONFIG_SYS_DDR_RAW_TIMING
540 if (!j && retval) {
541 printf("SPD error on controller %d! "
542 "Trying fallback to raw timing "
543 "calculation\n", i);
544 retval = fsl_ddr_get_dimm_params(pdimm,
545 i, j);
546 }
547 #else
548 if (retval == 2) {
549 printf("Error: compute_dimm_parameters"
550 " non-zero returned FATAL value "
551 "for memctl=%u dimm=%u\n", i, j);
552 return 0;
553 }
554 #endif
555 if (retval) {
556 debug("Warning: compute_dimm_parameters"
557 " non-zero return value for memctl=%u "
558 "dimm=%u\n", i, j);
559 } else {
560 goodspd = true;
561 }
562 }
563 }
564 if (!goodspd) {
565 /*
566 * No valid SPD found
567 * Throw an error if this is for main memory, i.e.
568 * first_ctrl == 0. Otherwise, siliently return 0
569 * as the memory size.
570 */
571 if (first_ctrl == 0)
572 printf("Error: No valid SPD detected.\n");
573
574 return 0;
575 }
576 #elif defined(CONFIG_SYS_DDR_RAW_TIMING)
577 case STEP_COMPUTE_DIMM_PARMS:
578 for (i = first_ctrl; i <= last_ctrl; i++) {
579 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
580 dimm_params_t *pdimm =
581 &(pinfo->dimm_params[i][j]);
582 fsl_ddr_get_dimm_params(pdimm, i, j);
583 }
584 }
585 debug("Filling dimm parameters from board specific file\n");
586 #endif
587 case STEP_COMPUTE_COMMON_PARMS:
588 /*
589 * STEP 3: Compute a common set of timing parameters
590 * suitable for all of the DIMMs on each memory controller
591 */
592 for (i = first_ctrl; i <= last_ctrl; i++) {
593 debug("Computing lowest common DIMM"
594 " parameters for memctl=%u\n", i);
595 compute_lowest_common_dimm_parameters
596 (i,
597 pinfo->dimm_params[i],
598 &timing_params[i],
599 CONFIG_DIMM_SLOTS_PER_CTLR);
600 }
601
602 case STEP_GATHER_OPTS:
603 /* STEP 4: Gather configuration requirements from user */
604 for (i = first_ctrl; i <= last_ctrl; i++) {
605 debug("Reloading memory controller "
606 "configuration options for memctl=%u\n", i);
607 /*
608 * This "reloads" the memory controller options
609 * to defaults. If the user "edits" an option,
610 * next_step points to the step after this,
611 * which is currently STEP_ASSIGN_ADDRESSES.
612 */
613 populate_memctl_options(
614 &timing_params[i],
615 &pinfo->memctl_opts[i],
616 pinfo->dimm_params[i], i);
617 /*
618 * For RDIMMs, JEDEC spec requires clocks to be stable
619 * before reset signal is deasserted. For the boards
620 * using fixed parameters, this function should be
621 * be called from board init file.
622 */
623 if (timing_params[i].all_dimms_registered)
624 assert_reset = 1;
625 }
626 if (assert_reset && !size_only) {
627 if (pinfo->board_mem_reset) {
628 debug("Asserting mem reset\n");
629 pinfo->board_mem_reset();
630 } else {
631 debug("Asserting mem reset missing\n");
632 }
633 }
634
635 case STEP_ASSIGN_ADDRESSES:
636 /* STEP 5: Assign addresses to chip selects */
637 check_interleaving_options(pinfo);
638 total_mem = step_assign_addresses(pinfo, dbw_capacity_adjust);
639 debug("Total mem %llu assigned\n", total_mem);
640
641 case STEP_COMPUTE_REGS:
642 /* STEP 6: compute controller register values */
643 debug("FSL Memory ctrl register computation\n");
644 for (i = first_ctrl; i <= last_ctrl; i++) {
645 if (timing_params[i].ndimms_present == 0) {
646 memset(&ddr_reg[i], 0,
647 sizeof(fsl_ddr_cfg_regs_t));
648 continue;
649 }
650
651 compute_fsl_memctl_config_regs
652 (i,
653 &pinfo->memctl_opts[i],
654 &ddr_reg[i], &timing_params[i],
655 pinfo->dimm_params[i],
656 dbw_capacity_adjust[i],
657 size_only);
658 }
659
660 default:
661 break;
662 }
663
664 {
665 /*
666 * Compute the amount of memory available just by
667 * looking for the highest valid CSn_BNDS value.
668 * This allows us to also experiment with using
669 * only CS0 when using dual-rank DIMMs.
670 */
671 unsigned int max_end = 0;
672
673 for (i = first_ctrl; i <= last_ctrl; i++) {
674 for (j = 0; j < CONFIG_CHIP_SELECTS_PER_CTRL; j++) {
675 fsl_ddr_cfg_regs_t *reg = &ddr_reg[i];
676 if (reg->cs[j].config & 0x80000000) {
677 unsigned int end;
678 /*
679 * 0xfffffff is a special value we put
680 * for unused bnds
681 */
682 if (reg->cs[j].bnds == 0xffffffff)
683 continue;
684 end = reg->cs[j].bnds & 0xffff;
685 if (end > max_end) {
686 max_end = end;
687 }
688 }
689 }
690 }
691
692 total_mem = 1 + (((unsigned long long)max_end << 24ULL) |
693 0xFFFFFFULL) - pinfo->mem_base;
694 }
695
696 return total_mem;
697 }
698
__fsl_ddr_sdram(fsl_ddr_info_t * pinfo)699 phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo)
700 {
701 unsigned int i, first_ctrl, last_ctrl;
702 #ifdef CONFIG_PPC
703 unsigned int law_memctl = LAW_TRGT_IF_DDR_1;
704 #endif
705 unsigned long long total_memory;
706 int deassert_reset = 0;
707
708 first_ctrl = pinfo->first_ctrl;
709 last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
710
711 /* Compute it once normally. */
712 #ifdef CONFIG_FSL_DDR_INTERACTIVE
713 if (tstc() && (getchar() == 'd')) { /* we got a key press of 'd' */
714 total_memory = fsl_ddr_interactive(pinfo, 0);
715 } else if (fsl_ddr_interactive_env_var_exists()) {
716 total_memory = fsl_ddr_interactive(pinfo, 1);
717 } else
718 #endif
719 total_memory = fsl_ddr_compute(pinfo, STEP_GET_SPD, 0);
720
721 /* setup 3-way interleaving before enabling DDRC */
722 switch (pinfo->memctl_opts[first_ctrl].memctl_interleaving_mode) {
723 case FSL_DDR_3WAY_1KB_INTERLEAVING:
724 case FSL_DDR_3WAY_4KB_INTERLEAVING:
725 case FSL_DDR_3WAY_8KB_INTERLEAVING:
726 fsl_ddr_set_intl3r(
727 pinfo->memctl_opts[first_ctrl].
728 memctl_interleaving_mode);
729 break;
730 default:
731 break;
732 }
733
734 /*
735 * Program configuration registers.
736 * JEDEC specs requires clocks to be stable before deasserting reset
737 * for RDIMMs. Clocks start after chip select is enabled and clock
738 * control register is set. During step 1, all controllers have their
739 * registers set but not enabled. Step 2 proceeds after deasserting
740 * reset through board FPGA or GPIO.
741 * For non-registered DIMMs, initialization can go through but it is
742 * also OK to follow the same flow.
743 */
744 if (pinfo->board_need_mem_reset)
745 deassert_reset = pinfo->board_need_mem_reset();
746 for (i = first_ctrl; i <= last_ctrl; i++) {
747 if (pinfo->common_timing_params[i].all_dimms_registered)
748 deassert_reset = 1;
749 }
750 for (i = first_ctrl; i <= last_ctrl; i++) {
751 debug("Programming controller %u\n", i);
752 if (pinfo->common_timing_params[i].ndimms_present == 0) {
753 debug("No dimms present on controller %u; "
754 "skipping programming\n", i);
755 continue;
756 }
757 /*
758 * The following call with step = 1 returns before enabling
759 * the controller. It has to finish with step = 2 later.
760 */
761 fsl_ddr_set_memctl_regs(&(pinfo->fsl_ddr_config_reg[i]), i,
762 deassert_reset ? 1 : 0);
763 }
764 if (deassert_reset) {
765 /* Use board FPGA or GPIO to deassert reset signal */
766 if (pinfo->board_mem_de_reset) {
767 debug("Deasserting mem reset\n");
768 pinfo->board_mem_de_reset();
769 } else {
770 debug("Deasserting mem reset missing\n");
771 }
772 for (i = first_ctrl; i <= last_ctrl; i++) {
773 /* Call with step = 2 to continue initialization */
774 fsl_ddr_set_memctl_regs(&(pinfo->fsl_ddr_config_reg[i]),
775 i, 2);
776 }
777 }
778
779 #ifdef CONFIG_FSL_DDR_SYNC_REFRESH
780 fsl_ddr_sync_memctl_refresh(first_ctrl, last_ctrl);
781 #endif
782
783 #ifdef CONFIG_PPC
784 /* program LAWs */
785 for (i = first_ctrl; i <= last_ctrl; i++) {
786 if (pinfo->memctl_opts[i].memctl_interleaving) {
787 switch (pinfo->memctl_opts[i].
788 memctl_interleaving_mode) {
789 case FSL_DDR_CACHE_LINE_INTERLEAVING:
790 case FSL_DDR_PAGE_INTERLEAVING:
791 case FSL_DDR_BANK_INTERLEAVING:
792 case FSL_DDR_SUPERBANK_INTERLEAVING:
793 if (i % 2)
794 break;
795 if (i == 0) {
796 law_memctl = LAW_TRGT_IF_DDR_INTRLV;
797 fsl_ddr_set_lawbar(
798 &pinfo->common_timing_params[i],
799 law_memctl, i);
800 }
801 #if CONFIG_SYS_NUM_DDR_CTLRS > 3
802 else if (i == 2) {
803 law_memctl = LAW_TRGT_IF_DDR_INTLV_34;
804 fsl_ddr_set_lawbar(
805 &pinfo->common_timing_params[i],
806 law_memctl, i);
807 }
808 #endif
809 break;
810 case FSL_DDR_3WAY_1KB_INTERLEAVING:
811 case FSL_DDR_3WAY_4KB_INTERLEAVING:
812 case FSL_DDR_3WAY_8KB_INTERLEAVING:
813 law_memctl = LAW_TRGT_IF_DDR_INTLV_123;
814 if (i == 0) {
815 fsl_ddr_set_lawbar(
816 &pinfo->common_timing_params[i],
817 law_memctl, i);
818 }
819 break;
820 case FSL_DDR_4WAY_1KB_INTERLEAVING:
821 case FSL_DDR_4WAY_4KB_INTERLEAVING:
822 case FSL_DDR_4WAY_8KB_INTERLEAVING:
823 law_memctl = LAW_TRGT_IF_DDR_INTLV_1234;
824 if (i == 0)
825 fsl_ddr_set_lawbar(
826 &pinfo->common_timing_params[i],
827 law_memctl, i);
828 /* place holder for future 4-way interleaving */
829 break;
830 default:
831 break;
832 }
833 } else {
834 switch (i) {
835 case 0:
836 law_memctl = LAW_TRGT_IF_DDR_1;
837 break;
838 case 1:
839 law_memctl = LAW_TRGT_IF_DDR_2;
840 break;
841 case 2:
842 law_memctl = LAW_TRGT_IF_DDR_3;
843 break;
844 case 3:
845 law_memctl = LAW_TRGT_IF_DDR_4;
846 break;
847 default:
848 break;
849 }
850 fsl_ddr_set_lawbar(&pinfo->common_timing_params[i],
851 law_memctl, i);
852 }
853 }
854 #endif
855
856 debug("total_memory by %s = %llu\n", __func__, total_memory);
857
858 #if !defined(CONFIG_PHYS_64BIT)
859 /*
860 * Show warning about big DDR moodules. But avoid warning for 4 GB DDR
861 * modules when U-Boot supports RAM of maximal size 4 GB - 1 byte.
862 */
863 if ((first_ctrl == 0) && (total_memory - 1 > (phys_size_t)~0ULL)) {
864 puts("Detected ");
865 print_size(total_memory, " of memory\n");
866 #ifndef CONFIG_XPL_BUILD
867 puts(" "); /* re-align to match init_dram print */
868 #endif
869 puts("This U-Boot only supports <= ");
870 print_size((unsigned long long)((phys_size_t)~0ULL)+1, " of DDR\n");
871 #ifndef CONFIG_XPL_BUILD
872 puts(" "); /* re-align to match init_dram print */
873 #endif
874 puts("You could rebuild it with CONFIG_PHYS_64BIT\n");
875 #ifndef CONFIG_XPL_BUILD
876 puts(" "); /* re-align to match init_dram print */
877 #endif
878 }
879 #endif
880
881 /* Ensure that total_memory does not overflow on return */
882 if (total_memory > (phys_size_t)~0ULL)
883 total_memory = (phys_size_t)~0ULL;
884
885 return total_memory;
886 }
887
888 /*
889 * fsl_ddr_sdram(void) -- this is the main function to be
890 * called by dram_init() in the board file.
891 *
892 * It returns amount of memory configured in bytes.
893 */
fsl_ddr_sdram(void)894 phys_size_t fsl_ddr_sdram(void)
895 {
896 fsl_ddr_info_t info;
897
898 /* Reset info structure. */
899 memset(&info, 0, sizeof(fsl_ddr_info_t));
900 info.mem_base = CFG_SYS_FSL_DDR_SDRAM_BASE_PHY;
901 info.first_ctrl = 0;
902 info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS;
903 info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR;
904 info.board_need_mem_reset = board_need_mem_reset;
905 info.board_mem_reset = board_assert_mem_reset;
906 info.board_mem_de_reset = board_deassert_mem_reset;
907 remove_unused_controllers(&info);
908
909 return __fsl_ddr_sdram(&info);
910 }
911
912 #ifdef CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
fsl_other_ddr_sdram(unsigned long long base,unsigned int first_ctrl,unsigned int num_ctrls,unsigned int dimm_slots_per_ctrl,int (* board_need_reset)(void),void (* board_reset)(void),void (* board_de_reset)(void))913 phys_size_t fsl_other_ddr_sdram(unsigned long long base,
914 unsigned int first_ctrl,
915 unsigned int num_ctrls,
916 unsigned int dimm_slots_per_ctrl,
917 int (*board_need_reset)(void),
918 void (*board_reset)(void),
919 void (*board_de_reset)(void))
920 {
921 fsl_ddr_info_t info;
922
923 /* Reset info structure. */
924 memset(&info, 0, sizeof(fsl_ddr_info_t));
925 info.mem_base = base;
926 info.first_ctrl = first_ctrl;
927 info.num_ctrls = num_ctrls;
928 info.dimm_slots_per_ctrl = dimm_slots_per_ctrl;
929 info.board_need_mem_reset = board_need_reset;
930 info.board_mem_reset = board_reset;
931 info.board_mem_de_reset = board_de_reset;
932
933 return __fsl_ddr_sdram(&info);
934 }
935 #endif
936
937 /*
938 * fsl_ddr_sdram_size(first_ctrl, last_intlv) - This function only returns the
939 * size of the total memory without setting ddr control registers.
940 */
941 phys_size_t
fsl_ddr_sdram_size(void)942 fsl_ddr_sdram_size(void)
943 {
944 fsl_ddr_info_t info;
945 unsigned long long total_memory = 0;
946
947 memset(&info, 0 , sizeof(fsl_ddr_info_t));
948 info.mem_base = CFG_SYS_FSL_DDR_SDRAM_BASE_PHY;
949 info.first_ctrl = 0;
950 info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS;
951 info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR;
952 info.board_need_mem_reset = NULL;
953 remove_unused_controllers(&info);
954
955 /* Compute it once normally. */
956 total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1);
957
958 /* Ensure that total_memory does not overflow on return */
959 if (total_memory > (phys_size_t)~0ULL)
960 total_memory = (phys_size_t)~0ULL;
961
962 return total_memory;
963 }
964