1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright 2018 NXP
4  */
5 
6 #include <errno.h>
7 #include <log.h>
8 #include <asm/io.h>
9 #include <asm/arch/ddr.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/ddr.h>
12 #include <asm/arch/sys_proto.h>
13 
poll_pmu_message_ready(void)14 static inline void poll_pmu_message_ready(void)
15 {
16 	unsigned int reg;
17 
18 	do {
19 		reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0004));
20 	} while (reg & 0x1);
21 }
22 
ack_pmu_message_receive(void)23 static inline void ack_pmu_message_receive(void)
24 {
25 	unsigned int reg;
26 
27 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0031), 0x0);
28 
29 	do {
30 		reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0004));
31 	} while (!(reg & 0x1));
32 
33 	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0031), 0x1);
34 }
35 
get_mail(void)36 static inline unsigned int get_mail(void)
37 {
38 	unsigned int reg;
39 
40 	poll_pmu_message_ready();
41 
42 	reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0032));
43 
44 	ack_pmu_message_receive();
45 
46 	return reg;
47 }
48 
get_stream_message(void)49 static inline unsigned int get_stream_message(void)
50 {
51 	unsigned int reg, reg2;
52 
53 	poll_pmu_message_ready();
54 
55 	reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0032));
56 
57 	reg2 = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0034));
58 
59 	reg2 = (reg2 << 16) | reg;
60 
61 	ack_pmu_message_receive();
62 
63 	return reg2;
64 }
65 
decode_major_message(unsigned int mail)66 static inline void decode_major_message(unsigned int mail)
67 {
68 	debug("[PMU Major message = 0x%08x]\n", mail);
69 }
70 
decode_streaming_message(void)71 static inline void decode_streaming_message(void)
72 {
73 	unsigned int string_index, arg __maybe_unused;
74 	int i = 0;
75 
76 	string_index = get_stream_message();
77 	debug("PMU String index = 0x%08x\n", string_index);
78 	while (i < (string_index & 0xffff)) {
79 		arg = get_stream_message();
80 		debug("arg[%d] = 0x%08x\n", i, arg);
81 		i++;
82 	}
83 
84 	debug("\n");
85 }
86 
wait_ddrphy_training_complete(void)87 int wait_ddrphy_training_complete(void)
88 {
89 	unsigned int mail;
90 
91 	while (1) {
92 		mail = get_mail();
93 		decode_major_message(mail);
94 		if (mail == 0x08) {
95 			decode_streaming_message();
96 		} else if (mail == 0x07) {
97 			debug("Training PASS\n");
98 			return 0;
99 		} else if (mail == 0xff) {
100 			printf("Training FAILED\n");
101 			return -1;
102 		}
103 	}
104 }
105 
ddrphy_init_set_dfi_clk(unsigned int drate)106 void ddrphy_init_set_dfi_clk(unsigned int drate)
107 {
108 	switch (drate) {
109 	case 4000:
110 		dram_pll_init(MHZ(1000));
111 		dram_disable_bypass();
112 		break;
113 	case 3734:
114 	case 3733:
115 	case 3732:
116 		dram_pll_init(MHZ(933));
117 		dram_disable_bypass();
118 		break;
119 	case 3600:
120 		dram_pll_init(MHZ(900));
121 		dram_disable_bypass();
122 		break;
123 	case 3200:
124 		dram_pll_init(MHZ(800));
125 		dram_disable_bypass();
126 		break;
127 	case 3000:
128 		dram_pll_init(MHZ(750));
129 		dram_disable_bypass();
130 		break;
131 	case 2800:
132 		dram_pll_init(MHZ(700));
133 		dram_disable_bypass();
134 		break;
135 	case 2400:
136 		dram_pll_init(MHZ(600));
137 		dram_disable_bypass();
138 		break;
139 	case 1866:
140 		dram_pll_init(MHZ(466));
141 		dram_disable_bypass();
142 		break;
143 	case 1600:
144 		dram_pll_init(MHZ(400));
145 		dram_disable_bypass();
146 		break;
147 	case 1200:
148 		dram_pll_init(MHZ(300));
149 		dram_disable_bypass();
150 		break;
151 	case 1066:
152 		dram_pll_init(MHZ(266));
153 		dram_disable_bypass();
154 		break;
155 	case 933:
156 		dram_pll_init(MHZ(233));
157 		dram_disable_bypass();
158 		break;
159 	case 800:
160 		dram_pll_init(MHZ(200));
161 		dram_disable_bypass();
162 		break;
163 	case 667:
164 		dram_pll_init(MHZ(167));
165 		dram_disable_bypass();
166 		break;
167 	case 625:
168 		dram_enable_bypass(MHZ(625));
169 		break;
170 	case 400:
171 		dram_enable_bypass(MHZ(400));
172 		break;
173 	case 333:
174 		dram_enable_bypass(MHZ(333));
175 		break;
176 	case 200:
177 		dram_enable_bypass(MHZ(200));
178 		break;
179 	case 100:
180 		dram_enable_bypass(MHZ(100));
181 		break;
182 	default:
183 		return;
184 	}
185 }
186 
ddrphy_init_read_msg_block(enum fw_type type)187 void ddrphy_init_read_msg_block(enum fw_type type)
188 {
189 }
190