1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2004,2007,2008 Freescale Semiconductor, Inc.
4 * (C) Copyright 2002, 2003 Motorola Inc.
5 * Xianghua Xiao (X.Xiao@motorola.com)
6 *
7 * (C) Copyright 2000
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 */
10
11 #include <config.h>
12 #include <asm/io.h>
13 #include <asm/fsl_dma.h>
14
15 /* Controller can only transfer 2^26 - 1 bytes at a time */
16 #define FSL_DMA_MAX_SIZE (0x3ffffff)
17
18 #if defined(CONFIG_MPC83xx)
19 #define FSL_DMA_MR_DEFAULT (FSL_DMA_MR_CTM_DIRECT | FSL_DMA_MR_DMSEN)
20 #else
21 #define FSL_DMA_MR_DEFAULT (FSL_DMA_MR_BWC_DIS | FSL_DMA_MR_CTM_DIRECT)
22 #endif
23
24 #if defined(CONFIG_MPC83xx)
25 dma83xx_t *dma_base = (void *)(CFG_SYS_MPC83xx_DMA_ADDR);
26 #elif defined(CONFIG_MPC85xx)
27 ccsr_dma_t *dma_base = (void *)(CFG_SYS_MPC85xx_DMA_ADDR);
28 #elif defined(CONFIG_MPC86xx)
29 ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
30 #else
31 #error "Freescale DMA engine not supported on your processor"
32 #endif
33
dma_sync(void)34 static void dma_sync(void)
35 {
36 #if defined(CONFIG_MPC85xx)
37 asm("sync; isync; msync");
38 #elif defined(CONFIG_MPC86xx)
39 asm("sync; isync");
40 #endif
41 }
42
out_dma32(volatile unsigned * addr,int val)43 static void out_dma32(volatile unsigned *addr, int val)
44 {
45 #if defined(CONFIG_MPC83xx)
46 out_le32(addr, val);
47 #else
48 out_be32(addr, val);
49 #endif
50 }
51
in_dma32(volatile unsigned * addr)52 static uint in_dma32(volatile unsigned *addr)
53 {
54 #if defined(CONFIG_MPC83xx)
55 return in_le32(addr);
56 #else
57 return in_be32(addr);
58 #endif
59 }
60
dma_check(void)61 static uint dma_check(void) {
62 volatile fsl_dma_t *dma = &dma_base->dma[0];
63 uint status;
64
65 /* While the channel is busy, spin */
66 do {
67 status = in_dma32(&dma->sr);
68 } while (status & FSL_DMA_SR_CB);
69
70 /* clear MR[CS] channel start bit */
71 out_dma32(&dma->mr, in_dma32(&dma->mr) & ~FSL_DMA_MR_CS);
72 dma_sync();
73
74 if (status != 0)
75 printf ("DMA Error: status = %x\n", status);
76
77 return status;
78 }
79
80 #if !defined(CONFIG_MPC83xx)
dma_init(void)81 void dma_init(void) {
82 volatile fsl_dma_t *dma = &dma_base->dma[0];
83
84 out_dma32(&dma->satr, FSL_DMA_SATR_SREAD_SNOOP);
85 out_dma32(&dma->datr, FSL_DMA_DATR_DWRITE_SNOOP);
86 out_dma32(&dma->sr, 0xffffffff); /* clear any errors */
87 dma_sync();
88 }
89 #endif
90
dmacpy(phys_addr_t dest,phys_addr_t src,phys_size_t count)91 int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t count) {
92 volatile fsl_dma_t *dma = &dma_base->dma[0];
93 uint xfer_size;
94
95 while (count) {
96 xfer_size = min(FSL_DMA_MAX_SIZE, count);
97
98 out_dma32(&dma->dar, (u32) (dest & 0xFFFFFFFF));
99 out_dma32(&dma->sar, (u32) (src & 0xFFFFFFFF));
100 #if !defined(CONFIG_MPC83xx)
101 out_dma32(&dma->satr,
102 in_dma32(&dma->satr) | (u32)((u64)src >> 32));
103 out_dma32(&dma->datr,
104 in_dma32(&dma->datr) | (u32)((u64)dest >> 32));
105 #endif
106 out_dma32(&dma->bcr, xfer_size);
107 dma_sync();
108
109 /* Prepare mode register */
110 out_dma32(&dma->mr, FSL_DMA_MR_DEFAULT);
111 dma_sync();
112
113 /* Start the transfer */
114 out_dma32(&dma->mr, FSL_DMA_MR_DEFAULT | FSL_DMA_MR_CS);
115
116 count -= xfer_size;
117 src += xfer_size;
118 dest += xfer_size;
119
120 dma_sync();
121
122 if (dma_check())
123 return -1;
124 }
125
126 return 0;
127 }
128
129 /*
130 * 85xx/86xx use dma to initialize SDRAM when !CONFIG_ECC_INIT_VIA_DDRCONTROLLER
131 */
132 #if ((!defined CONFIG_MPC83xx && defined(CONFIG_DDR_ECC) && \
133 !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)))
dma_meminit(uint size)134 void dma_meminit(uint size)
135 {
136 uint *p = 0;
137 uint i = 0;
138
139 for (*p = 0; p < (uint *)(8 * 1024); p++) {
140 if (((uint)p & 0x1f) == 0)
141 ppcDcbz((ulong)p);
142
143 *p = (uint)0xDEADBEEF;
144
145 if (((uint)p & 0x1c) == 0x1c)
146 ppcDcbf((ulong)p);
147 }
148
149 dmacpy(0x002000, 0, 0x002000); /* 8K */
150 dmacpy(0x004000, 0, 0x004000); /* 16K */
151 dmacpy(0x008000, 0, 0x008000); /* 32K */
152 dmacpy(0x010000, 0, 0x010000); /* 64K */
153 dmacpy(0x020000, 0, 0x020000); /* 128K */
154 dmacpy(0x040000, 0, 0x040000); /* 256K */
155 dmacpy(0x080000, 0, 0x080000); /* 512K */
156 dmacpy(0x100000, 0, 0x100000); /* 1M */
157 dmacpy(0x200000, 0, 0x200000); /* 2M */
158 dmacpy(0x400000, 0, 0x400000); /* 4M */
159
160 for (i = 1; i < size / 0x800000; i++)
161 dmacpy((0x800000 * i), 0, 0x800000);
162 }
163 #endif
164