1menu "FPGA support"
2
3config FPGA
4	bool
5
6config FPGA_ALTERA
7	bool "Enable Altera FPGA drivers"
8	select FPGA
9	help
10	  Say Y here to enable the Altera FPGA driver
11
12	  This provides basic infrastructure to support Altera FPGA devices.
13	  Enable Altera FPGA specific functions which includes bitstream
14	  (in BIT format), fpga and device validation.
15
16config FPGA_SOCFPGA
17	bool "Enable Gen5 and Arria10 common FPGA drivers"
18	depends on ARCH_SOCFPGA
19	select FPGA_ALTERA
20	help
21	  Say Y here to enable the Gen5 and Arria10 common FPGA driver
22
23	  This provides common functionality for Gen5 and Arria10 devices.
24
25config FPGA_STRATIX_II
26	bool "Enable Stratix II FPGA drivers"
27	depends on FPGA_ALTERA
28	help
29	  Say Y here to enable the Altera Stratix II FPGA-specific driver.
30
31config FPGA_STRATIX_V
32	bool "Enable Stratix V FPGA drivers"
33	depends on FPGA_ALTERA
34	help
35	  Say Y here to enable the Altera Stratix V FPGA specific driver.
36
37config FPGA_ACEX1K
38	bool "Enable Altera ACEX 1K driver"
39	depends on FPGA_ALTERA
40	help
41	  Say Y here to enable the Altera ACEX 1K FPGA specific driver.
42
43config FPGA_CYCLON2
44	bool "Enable Altera FPGA driver for Cyclone II"
45	depends on FPGA_ALTERA
46	help
47	  Say Y here to enable the Altera Cyclone II FPGA specific driver
48
49	  This provides common functionality for Altera Cyclone II devices.
50	  Enable FPGA driver for loading bitstream in BIT and BIN format
51	  on Altera Cyclone II device.
52
53config FPGA_INTEL_SDM_MAILBOX
54	bool "Enable Intel FPGA Full Reconfiguration SDM Mailbox driver"
55	depends on TARGET_SOCFPGA_SOC64
56	select FPGA_ALTERA
57	help
58	  Say Y here to enable the Intel FPGA Full Reconfig SDM Mailbox driver
59
60	  This provides common functionality for Intel FPGA devices.
61	  Enable FPGA driver for writing full bitstream into Intel FPGA
62	  devices through SDM (Secure Device Manager) Mailbox.
63
64config FPGA_LATTICE
65	bool "Enable Lattice FPGA driver"
66	help
67	  This is used for the lattice FPGAs. Please check the source code as
68	  there is no documentation for this at present.
69
70config FPGA_XILINX
71	bool "Enable Xilinx FPGA drivers"
72	select FPGA
73	help
74	  Enable Xilinx FPGA specific functions which includes bitstream
75	  (in BIT format), fpga and device validation.
76
77config FPGA_ZYNQMPPL
78	bool "Enable Xilinx FPGA driver for ZynqMP"
79	depends on FPGA_XILINX && ZYNQMP_FIRMWARE
80	help
81	  Enable FPGA driver for loading bitstream in BIT and BIN format
82	  on Xilinx Zynq UltraScale+ (ZynqMP) device.
83
84config FPGA_VERSALPL
85	bool "Enable Xilinx FPGA driver for Versal"
86	depends on FPGA_XILINX
87	help
88	  Enable FPGA driver for loading bitstream in PDI format on Xilinx
89	  Versal device. PDI is a new programmable device image format for
90	  Versal. The bitstream will only be generated as PDI for Versal
91	  platform.
92
93config FPGA_SPARTAN2
94	bool "Enable Spartan2 FPGA driver"
95	depends on FPGA_XILINX
96	help
97	  Enable Spartan2 FPGA driver.
98
99config FPGA_SPARTAN3
100	bool "Enable Spartan3 FPGA driver"
101	depends on FPGA_XILINX
102	help
103	  Enable Spartan3 FPGA driver for loading in BIT format.
104
105config FPGA_VIRTEX2
106	bool "Enable Xilinx Virtex-II and later FPGA driver"
107	depends on FPGA_XILINX
108	help
109	  Enable Virtex-II FPGA driver for loading in BIT format. This driver
110	  also supports many newer Xilinx FPGA families.
111
112config SYS_FPGA_CHECK_BUSY
113	bool "Perform busy check during load from FPGA"
114	depends on FPGA_SPARTAN2 || FPGA_SPARTAN3 || FPGA_VIRTEX2
115
116config FPGA_ZYNQPL
117	bool "Enable Xilinx FPGA for Zynq"
118	depends on ARCH_ZYNQ
119	help
120	  Enable FPGA driver for loading bitstream in BIT and BIN format
121	  on Xilinx Zynq devices.
122
123config SYS_FPGA_CHECK_CTRLC
124	bool "Allow Control-C to interrupt FPGA configuration"
125	depends on FPGA
126	help
127	  User can interrupt FPGA configuration by pressing CTRL+C.
128
129config SYS_FPGA_PROG_FEEDBACK
130	bool "Progress output during FPGA configuration"
131	depends on FPGA
132	default y if FPGA_VIRTEX2
133	help
134	  Enable printing of hash marks during FPGA configuration.
135
136config FPGA_LOAD_SECURE
137	bool "Enable loading secure bitstreams"
138	depends on FPGA
139	help
140	  Enables the fpga loads() functions that are used to load secure
141	  (authenticated or encrypted or both) bitstreams on to FPGA.
142
143config SPL_FPGA_LOAD_SECURE
144	bool "Enable loading secure bitstreams for SPL"
145	depends on SPL_FPGA
146	help
147	  Enables the fpga loads() functions that are used to load secure
148	  (authenticated or encrypted or both) bitstreams on to FPGA.
149
150config DM_FPGA
151	bool "Enable Driver Model for FPGA drivers"
152	depends on DM
153	select FPGA
154	help
155	  Enable driver model for Field-Programmable Gate Array (FPGA) devices.
156	  The devices cover a wide range of applications and are configured at
157	  runtime by loading a bitstream into the FPGA device.
158	  Loading a bitstream from any kind of storage is the main task of the
159	  FPGA drivers.
160	  For now this uclass has no methods yet.
161
162config SANDBOX_FPGA
163	bool "Enable sandbox FPGA driver"
164	depends on SANDBOX && DM_FPGA
165	help
166	  This is a driver model based FPGA driver for sandbox.
167	  Currently it is a stub only, as there are no usable uclass methods yet.
168
169config MAX_FPGA_DEVICES
170	int "Maximum number of FPGA devices"
171	depends on FPGA
172	default 5
173
174endmenu
175