1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2003
4 * Steven Scholz, imc Measurement & Control, steven.scholz@imc-berlin.de
5 *
6 * (C) Copyright 2002
7 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
8 */
9
10 #define LOG_CATEGORY UCLASS_FPGA
11
12 /*
13 * Altera FPGA support
14 */
15 #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \
16 IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10)
17 #include <asm/arch/misc.h>
18 #endif
19 #include <errno.h>
20 #include <ACEX1K.h>
21 #include <log.h>
22 #include <stratixII.h>
23
24 static const struct altera_fpga {
25 enum altera_family family;
26 const char *name;
27 int (*load)(Altera_desc *, const void *, size_t);
28 int (*dump)(Altera_desc *, const void *, size_t);
29 int (*info)(Altera_desc *);
30 } altera_fpga[] = {
31 #if defined(CONFIG_FPGA_ACEX1K)
32 { Altera_ACEX1K, "ACEX1K", ACEX1K_load, ACEX1K_dump, ACEX1K_info },
33 { Altera_CYC2, "ACEX1K", ACEX1K_load, ACEX1K_dump, ACEX1K_info },
34 #elif defined(CONFIG_FPGA_CYCLON2)
35 { Altera_ACEX1K, "CycloneII", CYC2_load, CYC2_dump, CYC2_info },
36 { Altera_CYC2, "CycloneII", CYC2_load, CYC2_dump, CYC2_info },
37 #endif
38 #if defined(CONFIG_FPGA_STRATIX_II)
39 { Altera_StratixII, "StratixII", StratixII_load,
40 StratixII_dump, StratixII_info },
41 #endif
42 #if defined(CONFIG_FPGA_STRATIX_V)
43 { Altera_StratixV, "StratixV", stratixv_load, NULL, NULL },
44 #endif
45 #if defined(CONFIG_FPGA_SOCFPGA)
46 { Altera_SoCFPGA, "SoC FPGA", socfpga_load, NULL, NULL },
47 #endif
48 #if defined(CONFIG_FPGA_INTEL_SDM_MAILBOX)
49 { Intel_FPGA_SDM_Mailbox, "Intel SDM Mailbox", intel_sdm_mb_load, NULL,
50 NULL },
51 #endif
52 };
53
54 #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \
55 IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10)
fpga_is_partial_data(int devnum,size_t img_len)56 int fpga_is_partial_data(int devnum, size_t img_len)
57 {
58 /*
59 * The FPGA data (full or partial) is checked by
60 * the SDM hardware, for Intel SDM Mailbox based
61 * devices. Hence always return full bitstream.
62 *
63 * For Cyclone V and Arria 10 family, the bitstream
64 * type parameter is not handled by the driver.
65 */
66 return 0;
67 }
68
fpga_loadbitstream(int devnum,char * fpgadata,size_t size,bitstream_type bstype)69 int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
70 bitstream_type bstype)
71 {
72 int ret_val;
73 int flags = 0;
74
75 ret_val = fpga_load(devnum, (void *)fpgadata, size, bstype, flags);
76
77 /*
78 * Enable the HPS to FPGA bridges when FPGA load is completed
79 * successfully. This is to ensure the FPGA is accessible
80 * by the HPS.
81 */
82 if (!ret_val) {
83 printf("Enable FPGA bridges\n");
84 do_bridge_reset(1, ~0);
85 }
86
87 return ret_val;
88 }
89 #endif
90
altera_validate(Altera_desc * desc,const char * fn)91 static int altera_validate(Altera_desc *desc, const char *fn)
92 {
93 if (!desc) {
94 printf("%s: NULL descriptor!\n", fn);
95 return -EINVAL;
96 }
97
98 if ((desc->family < min_altera_type) ||
99 (desc->family > max_altera_type)) {
100 printf("%s: Invalid family type, %d\n", fn, desc->family);
101 return -EINVAL;
102 }
103
104 if ((desc->iface < min_altera_iface_type) ||
105 (desc->iface > max_altera_iface_type)) {
106 printf("%s: Invalid Interface type, %d\n", fn, desc->iface);
107 return -EINVAL;
108 }
109
110 if (!desc->size) {
111 printf("%s: NULL part size\n", fn);
112 return -EINVAL;
113 }
114
115 return 0;
116 }
117
118 static const struct altera_fpga *
altera_desc_to_fpga(Altera_desc * desc,const char * fn)119 altera_desc_to_fpga(Altera_desc *desc, const char *fn)
120 {
121 int i;
122
123 if (altera_validate(desc, fn)) {
124 printf("%s: Invalid device descriptor\n", fn);
125 return NULL;
126 }
127
128 for (i = 0; i < ARRAY_SIZE(altera_fpga); i++) {
129 if (desc->family == altera_fpga[i].family)
130 break;
131 }
132
133 if (i == ARRAY_SIZE(altera_fpga)) {
134 printf("%s: Unsupported family type, %d\n", fn, desc->family);
135 return NULL;
136 }
137
138 return &altera_fpga[i];
139 }
140
altera_load(Altera_desc * desc,const void * buf,size_t bsize)141 int altera_load(Altera_desc *desc, const void *buf, size_t bsize)
142 {
143 const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__);
144
145 if (!fpga)
146 return FPGA_FAIL;
147
148 log_debug("Launching the %s Loader...\n", fpga->name);
149 if (fpga->load)
150 return fpga->load(desc, buf, bsize);
151 return 0;
152 }
153
altera_dump(Altera_desc * desc,const void * buf,size_t bsize)154 int altera_dump(Altera_desc *desc, const void *buf, size_t bsize)
155 {
156 const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__);
157
158 if (!fpga)
159 return FPGA_FAIL;
160
161 log_debug("Launching the %s Reader...\n", fpga->name);
162 if (fpga->dump)
163 return fpga->dump(desc, buf, bsize);
164 return 0;
165 }
166
altera_info(Altera_desc * desc)167 int altera_info(Altera_desc *desc)
168 {
169 const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__);
170
171 if (!fpga)
172 return FPGA_FAIL;
173
174 printf("Family: \t%s\n", fpga->name);
175
176 printf("Interface type:\t");
177 switch (desc->iface) {
178 case passive_serial:
179 printf("Passive Serial (PS)\n");
180 break;
181 case passive_parallel_synchronous:
182 printf("Passive Parallel Synchronous (PPS)\n");
183 break;
184 case passive_parallel_asynchronous:
185 printf("Passive Parallel Asynchronous (PPA)\n");
186 break;
187 case passive_serial_asynchronous:
188 printf("Passive Serial Asynchronous (PSA)\n");
189 break;
190 case altera_jtag_mode: /* Not used */
191 printf("JTAG Mode\n");
192 break;
193 case fast_passive_parallel:
194 printf("Fast Passive Parallel (FPP)\n");
195 break;
196 case fast_passive_parallel_security:
197 printf("Fast Passive Parallel with Security (FPPS)\n");
198 break;
199 case secure_device_manager_mailbox:
200 puts("Secure Device Manager (SDM) Mailbox\n");
201 break;
202 /* Add new interface types here */
203 default:
204 printf("Unsupported interface type, %d\n", desc->iface);
205 }
206
207 printf("Device Size: \t%zd bytes\n"
208 "Cookie: \t0x%x (%d)\n",
209 desc->size, desc->cookie, desc->cookie);
210
211 if (desc->iface_fns) {
212 printf("Device Function Table @ 0x%p\n", desc->iface_fns);
213 if (fpga->info)
214 fpga->info(desc);
215 } else {
216 printf("No Device Function Table.\n");
217 }
218
219 return FPGA_SUCCESS;
220 }
221