1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2002
4 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
5 * Keith Outwater, keith_outwater@mvis.com
6 *
7 * Copyright (c) 2019 SED Systems, a division of Calian Ltd.
8 */
9
10 /*
11 * Configuration support for Xilinx Virtex2 devices. Based
12 * on spartan2.c (Rich Ireland, rireland@enterasys.com).
13 */
14
15 #define LOG_CATEGORY UCLASS_FPGA
16
17 #include <config.h>
18 #include <console.h>
19 #include <log.h>
20 #include <virtex2.h>
21 #include <linux/delay.h>
22 #include <time.h>
23
24 /*
25 * If the SelectMap interface can be overrun by the processor, enable
26 * CONFIG_SYS_FPGA_CHECK_BUSY and/or define CFG_FPGA_DELAY in the board
27 * configuration file and add board-specific support for checking BUSY status.
28 * By default, assume that the SelectMap interface cannot be overrun.
29 */
30
31 #ifndef CFG_FPGA_DELAY
32 #define CFG_FPGA_DELAY()
33 #endif
34
35 /*
36 * Check for errors during configuration by default
37 */
38 #ifndef CFG_SYS_FPGA_CHECK_ERROR
39 #define CFG_SYS_FPGA_CHECK_ERROR
40 #endif
41
42 /*
43 * The default timeout in mS for INIT_B to deassert after PROG_B has
44 * been deasserted. Per the latest Virtex II Handbook (page 347), the
45 * max time from PORG_B deassertion to INIT_B deassertion is 4uS per
46 * data frame for the XC2V8000. The XC2V8000 has 2860 data frames
47 * which yields 11.44 mS. So let's make it bigger in order to handle
48 * an XC2V1000, if anyone can ever get ahold of one.
49 */
50 #ifndef CFG_SYS_FPGA_WAIT_INIT
51 #define CFG_SYS_FPGA_WAIT_INIT CONFIG_SYS_HZ / 2 /* 500 ms */
52 #endif
53
54 /*
55 * The default timeout for waiting for BUSY to deassert during configuration.
56 * This is normally not necessary since for most reasonable configuration
57 * clock frequencies (i.e. 66 MHz or less), BUSY monitoring is unnecessary.
58 */
59 #ifndef CFG_SYS_FPGA_WAIT_BUSY
60 #define CFG_SYS_FPGA_WAIT_BUSY CONFIG_SYS_HZ / 200 /* 5 ms*/
61 #endif
62
63 /* Default timeout for waiting for FPGA to enter operational mode after
64 * configuration data has been written.
65 */
66 #ifndef CFG_SYS_FPGA_WAIT_CONFIG
67 #define CFG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ / 5 /* 200 ms */
68 #endif
69
70 static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize);
71 static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize);
72
73 static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize);
74 static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
75
virtex2_load(xilinx_desc * desc,const void * buf,size_t bsize,bitstream_type bstype,int flags)76 static int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize,
77 bitstream_type bstype, int flags)
78 {
79 int ret_val = FPGA_FAIL;
80
81 switch (desc->iface) {
82 case slave_serial:
83 log_debug("Launching Slave Serial Load\n");
84 ret_val = virtex2_ss_load(desc, buf, bsize);
85 break;
86
87 case slave_selectmap:
88 log_debug("Launching Slave Parallel Load\n");
89 ret_val = virtex2_ssm_load(desc, buf, bsize);
90 break;
91
92 default:
93 printf("%s: Unsupported interface type, %d\n",
94 __func__, desc->iface);
95 }
96 return ret_val;
97 }
98
virtex2_dump(xilinx_desc * desc,const void * buf,size_t bsize)99 static int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize)
100 {
101 int ret_val = FPGA_FAIL;
102
103 switch (desc->iface) {
104 case slave_serial:
105 log_debug("Launching Slave Serial Dump\n");
106 ret_val = virtex2_ss_dump(desc, buf, bsize);
107 break;
108
109 case slave_parallel:
110 log_debug("Launching Slave Parallel Dump\n");
111 ret_val = virtex2_ssm_dump(desc, buf, bsize);
112 break;
113
114 default:
115 printf("%s: Unsupported interface type, %d\n",
116 __func__, desc->iface);
117 }
118 return ret_val;
119 }
120
virtex2_info(xilinx_desc * desc)121 static int virtex2_info(xilinx_desc *desc)
122 {
123 return FPGA_SUCCESS;
124 }
125
126 /*
127 * Virtex-II Slave SelectMap or Serial configuration loader. Configuration
128 * is as follows:
129 * 1. Set the FPGA's PROG_B line low.
130 * 2. Set the FPGA's PROG_B line high. Wait for INIT_B to go high.
131 * 3. Write data to the SelectMap port. If INIT_B goes low at any time
132 * this process, a configuration error (most likely CRC failure) has
133 * ocurred. At this point a status word may be read from the
134 * SelectMap interface to determine the source of the problem (You
135 * could, for instance, put this in your 'abort' function handler).
136 * 4. After all data has been written, test the state of the FPGA
137 * INIT_B and DONE lines. If both are high, configuration has
138 * succeeded. Congratulations!
139 */
virtex2_slave_pre(xilinx_virtex2_slave_fns * fn,int cookie)140 static int virtex2_slave_pre(xilinx_virtex2_slave_fns *fn, int cookie)
141 {
142 unsigned long ts;
143
144 log_debug("Start with interface functions @ 0x%p\n", fn);
145
146 if (!fn) {
147 printf("%s:%d: NULL Interface function table!\n",
148 __func__, __LINE__);
149 return FPGA_FAIL;
150 }
151
152 /* Gotta split this one up (so the stack won't blow??) */
153 log_debug("Function Table:\n"
154 " base 0x%p\n"
155 " struct 0x%p\n"
156 " pre 0x%p\n"
157 " prog 0x%p\n"
158 " init 0x%p\n"
159 " error 0x%p\n",
160 &fn, fn, fn->pre, fn->pgm, fn->init, fn->err);
161 log_debug(" clock 0x%p\n"
162 " cs 0x%p\n"
163 " write 0x%p\n"
164 " rdata 0x%p\n"
165 " wdata 0x%p\n"
166 " busy 0x%p\n"
167 " abort 0x%p\n"
168 " post 0x%p\n\n",
169 fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata,
170 fn->busy, fn->abort, fn->post);
171
172 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
173 printf("Initializing FPGA Device %d...\n", cookie);
174 #endif
175 /*
176 * Run the pre configuration function if there is one.
177 */
178 if (*fn->pre)
179 (*fn->pre)(cookie);
180
181 /*
182 * Assert the program line. The minimum pulse width for
183 * Virtex II devices is 300 nS (Tprogram parameter in datasheet).
184 * There is no maximum value for the pulse width. Check to make
185 * sure that INIT_B goes low after assertion of PROG_B
186 */
187 (*fn->pgm)(true, true, cookie);
188 udelay(10);
189 ts = get_timer(0);
190 do {
191 if (get_timer(ts) > CFG_SYS_FPGA_WAIT_INIT) {
192 printf("%s:%d: ** Timeout after %d ticks waiting for INIT to assert.\n",
193 __func__, __LINE__, CFG_SYS_FPGA_WAIT_INIT);
194 (*fn->abort)(cookie);
195 return FPGA_FAIL;
196 }
197 } while (!(*fn->init)(cookie));
198
199 (*fn->pgm)(false, true, cookie);
200 CFG_FPGA_DELAY();
201 if (fn->clk)
202 (*fn->clk)(true, true, cookie);
203
204 /*
205 * Start a timer and wait for INIT_B to go high
206 */
207 ts = get_timer(0);
208 do {
209 CFG_FPGA_DELAY();
210 if (get_timer(ts) > CFG_SYS_FPGA_WAIT_INIT) {
211 printf("%s:%d: ** Timeout after %d ticks waiting for INIT to deassert.\n",
212 __func__, __LINE__, CFG_SYS_FPGA_WAIT_INIT);
213 (*fn->abort)(cookie);
214 return FPGA_FAIL;
215 }
216 } while ((*fn->init)(cookie) && (*fn->busy)(cookie));
217
218 if (fn->wr)
219 (*fn->wr)(true, true, cookie);
220 if (fn->cs)
221 (*fn->cs)(true, true, cookie);
222
223 mdelay(10);
224 return FPGA_SUCCESS;
225 }
226
virtex2_slave_post(xilinx_virtex2_slave_fns * fn,int cookie)227 static int virtex2_slave_post(xilinx_virtex2_slave_fns *fn,
228 int cookie)
229 {
230 int ret_val = FPGA_SUCCESS;
231 int num_done = 0;
232 unsigned long ts;
233
234 /*
235 * Finished writing the data; deassert FPGA CS_B and WRITE_B signals.
236 */
237 CFG_FPGA_DELAY();
238 if (fn->cs)
239 (*fn->cs)(false, true, cookie);
240 if (fn->wr)
241 (*fn->wr)(false, true, cookie);
242
243 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
244 putc('\n');
245 #endif
246
247 /*
248 * Check for successful configuration. FPGA INIT_B and DONE
249 * should both be high upon successful configuration. Continue pulsing
250 * clock with data set to all ones until DONE is asserted and for 8
251 * clock cycles afterwards.
252 */
253 ts = get_timer(0);
254 while (true) {
255 if ((*fn->done)(cookie) == FPGA_SUCCESS &&
256 !((*fn->init)(cookie))) {
257 if (num_done++ >= 8)
258 break;
259 }
260
261 if (get_timer(ts) > CFG_SYS_FPGA_WAIT_CONFIG) {
262 printf("%s:%d: ** Timeout after %d ticks waiting for DONE to assert and INIT to deassert\n",
263 __func__, __LINE__, CFG_SYS_FPGA_WAIT_CONFIG);
264 (*fn->abort)(cookie);
265 ret_val = FPGA_FAIL;
266 break;
267 }
268 if (fn->wbulkdata) {
269 unsigned char dummy = 0xff;
270 (*fn->wbulkdata)(&dummy, 1, true, cookie);
271 } else {
272 (*fn->wdata)(0xff, true, cookie);
273 CFG_FPGA_DELAY();
274 (*fn->clk)(false, true, cookie);
275 CFG_FPGA_DELAY();
276 (*fn->clk)(true, true, cookie);
277 }
278 }
279
280 if (ret_val == FPGA_SUCCESS) {
281 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
282 printf("Initialization of FPGA device %d complete\n", cookie);
283 #endif
284 /*
285 * Run the post configuration function if there is one.
286 */
287 if (*fn->post)
288 (*fn->post)(cookie);
289 } else {
290 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
291 printf("** Initialization of FPGA device %d FAILED\n",
292 cookie);
293 #endif
294 }
295 return ret_val;
296 }
297
virtex2_ssm_load(xilinx_desc * desc,const void * buf,size_t bsize)298 static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
299 {
300 int ret_val = FPGA_FAIL;
301 xilinx_virtex2_slave_fns *fn = desc->iface_fns;
302 size_t bytecount = 0;
303 unsigned char *data = (unsigned char *)buf;
304 int cookie = desc->cookie;
305 unsigned long ts;
306
307 ret_val = virtex2_slave_pre(fn, cookie);
308 if (ret_val != FPGA_SUCCESS)
309 return ret_val;
310
311 /*
312 * Load the data byte by byte
313 */
314 while (bytecount < bsize) {
315 #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
316 if (ctrlc()) {
317 (*fn->abort)(cookie);
318 return FPGA_FAIL;
319 }
320 #endif
321
322 if ((*fn->done)(cookie) == FPGA_SUCCESS) {
323 log_debug("done went active early, bytecount = %zu\n",
324 bytecount);
325 break;
326 }
327
328 #ifdef CFG_SYS_FPGA_CHECK_ERROR
329 if ((*fn->init)(cookie)) {
330 printf("\n%s:%d: ** Error: INIT asserted during configuration\n",
331 __func__, __LINE__);
332 printf("%zu = buffer offset, %zu = buffer size\n",
333 bytecount, bsize);
334 (*fn->abort)(cookie);
335 return FPGA_FAIL;
336 }
337 #endif
338
339 (*fn->wdata)(data[bytecount++], true, cookie);
340 CFG_FPGA_DELAY();
341
342 /*
343 * Cycle the clock pin
344 */
345 (*fn->clk)(false, true, cookie);
346 CFG_FPGA_DELAY();
347 (*fn->clk)(true, true, cookie);
348
349 #ifdef CONFIG_SYS_FPGA_CHECK_BUSY
350 ts = get_timer(0);
351 while ((*fn->busy)(cookie)) {
352 if (get_timer(ts) > CFG_SYS_FPGA_WAIT_BUSY) {
353 printf("%s:%d: ** Timeout after %d ticks waiting for BUSY to deassert\n",
354 __func__, __LINE__,
355 CFG_SYS_FPGA_WAIT_BUSY);
356 (*fn->abort)(cookie);
357 return FPGA_FAIL;
358 }
359 }
360 #endif
361
362 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
363 if (bytecount % (bsize / 40) == 0)
364 putc('.');
365 #endif
366 }
367
368 return virtex2_slave_post(fn, cookie);
369 }
370
371 /*
372 * Read the FPGA configuration data
373 */
virtex2_ssm_dump(xilinx_desc * desc,const void * buf,size_t bsize)374 static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize)
375 {
376 int ret_val = FPGA_FAIL;
377 xilinx_virtex2_slave_fns *fn = desc->iface_fns;
378
379 if (fn) {
380 unsigned char *data = (unsigned char *)buf;
381 size_t bytecount = 0;
382 int cookie = desc->cookie;
383
384 printf("Starting Dump of FPGA Device %d...\n", cookie);
385
386 (*fn->cs)(true, true, cookie);
387 (*fn->clk)(true, true, cookie);
388
389 while (bytecount < bsize) {
390 #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
391 if (ctrlc()) {
392 (*fn->abort)(cookie);
393 return FPGA_FAIL;
394 }
395 #endif
396 /*
397 * Cycle the clock and read the data
398 */
399 (*fn->clk)(false, true, cookie);
400 (*fn->clk)(true, true, cookie);
401 (*fn->rdata)(&data[bytecount++], cookie);
402 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
403 if (bytecount % (bsize / 40) == 0)
404 putc('.');
405 #endif
406 }
407
408 /*
409 * Deassert CS_B and cycle the clock to deselect the device.
410 */
411 (*fn->cs)(false, false, cookie);
412 (*fn->clk)(false, true, cookie);
413 (*fn->clk)(true, true, cookie);
414
415 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
416 putc('\n');
417 #endif
418 puts("Done.\n");
419 } else {
420 printf("%s:%d: NULL Interface function table!\n",
421 __func__, __LINE__);
422 }
423 return ret_val;
424 }
425
virtex2_ss_load(xilinx_desc * desc,const void * buf,size_t bsize)426 static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
427 {
428 int ret_val = FPGA_FAIL;
429 xilinx_virtex2_slave_fns *fn = desc->iface_fns;
430 unsigned char *data = (unsigned char *)buf;
431 int cookie = desc->cookie;
432
433 ret_val = virtex2_slave_pre(fn, cookie);
434 if (ret_val != FPGA_SUCCESS)
435 return ret_val;
436
437 if (fn->wbulkdata) {
438 /* Load the data in a single chunk */
439 (*fn->wbulkdata)(data, bsize, true, cookie);
440 } else {
441 size_t bytecount = 0;
442
443 /*
444 * Load the data bit by bit
445 */
446 while (bytecount < bsize) {
447 unsigned char curr_data = data[bytecount++];
448 int bit;
449
450 #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
451 if (ctrlc()) {
452 (*fn->abort) (cookie);
453 return FPGA_FAIL;
454 }
455 #endif
456
457 if ((*fn->done)(cookie) == FPGA_SUCCESS) {
458 log_debug("done went active early, bytecount = %zu\n",
459 bytecount);
460 break;
461 }
462
463 #ifdef CFG_SYS_FPGA_CHECK_ERROR
464 if ((*fn->init)(cookie)) {
465 printf("\n%s:%d: ** Error: INIT asserted during configuration\n",
466 __func__, __LINE__);
467 printf("%zu = buffer offset, %zu = buffer size\n",
468 bytecount, bsize);
469 (*fn->abort)(cookie);
470 return FPGA_FAIL;
471 }
472 #endif
473
474 for (bit = 7; bit >= 0; --bit) {
475 unsigned char curr_bit = (curr_data >> bit) & 1;
476 (*fn->wdata)(curr_bit, true, cookie);
477 CFG_FPGA_DELAY();
478 (*fn->clk)(false, true, cookie);
479 CFG_FPGA_DELAY();
480 (*fn->clk)(true, true, cookie);
481 }
482
483 /* Slave serial never uses a busy pin */
484
485 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
486 if (bytecount % (bsize / 40) == 0)
487 putc('.');
488 #endif
489 }
490 }
491
492 return virtex2_slave_post(fn, cookie);
493 }
494
virtex2_ss_dump(xilinx_desc * desc,const void * buf,size_t bsize)495 static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize)
496 {
497 printf("%s: Slave Serial Dumping is unsupported\n", __func__);
498 return FPGA_FAIL;
499 }
500
501 /* vim: set ts=4 tw=78: */
502
503 struct xilinx_fpga_op virtex2_op = {
504 .load = virtex2_load,
505 .dump = virtex2_dump,
506 .info = virtex2_info,
507 };
508