1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) ASPEED Technology Inc.
4 * Billy Tsai <billy_tsai@aspeedtech.com>
5 */
6 #include <asm/io.h>
7 #include <asm/gpio.h>
8
9 #include <config.h>
10 #include <clk.h>
11 #include <dm.h>
12 #include <dm/device_compat.h>
13 #include <asm/io.h>
14 #include <linux/bug.h>
15 #include <linux/sizes.h>
16 #include <linux/bitfield.h>
17 #include <linux/bitops.h>
18
19 #define ASPEED_SGPIO_CTRL 0x54
20
21 #define ASPEED_SGPIO_CLK_DIV_MASK GENMASK(31, 16)
22 #define ASPEED_SGPIO_ENABLE BIT(0)
23 #define ASPEED_SGPIO_PINS_SHIFT 6
24
25 struct aspeed_sgpio_priv {
26 void *base;
27 struct clk pclk;
28 const struct aspeed_sgpio_pdata *pdata;
29 };
30
31 struct aspeed_sgpio_pdata {
32 const u32 pin_mask;
33 const struct aspeed_sgpio_llops *llops;
34 };
35
36 struct aspeed_sgpio_bank {
37 u16 val_regs;
38 u16 rdata_reg;
39 u16 tolerance_regs;
40 const char names[4][3];
41 };
42
43 /*
44 * Note: The "value" register returns the input value when the GPIO is
45 * configured as an input.
46 *
47 * The "rdata" register returns the output value when the GPIO is
48 * configured as an output.
49 */
50 static const struct aspeed_sgpio_bank aspeed_sgpio_banks[] = {
51 {
52 .val_regs = 0x0000,
53 .rdata_reg = 0x0070,
54 .tolerance_regs = 0x0018,
55 .names = { "A", "B", "C", "D" },
56 },
57 {
58 .val_regs = 0x001C,
59 .rdata_reg = 0x0074,
60 .tolerance_regs = 0x0034,
61 .names = { "E", "F", "G", "H" },
62 },
63 {
64 .val_regs = 0x0038,
65 .rdata_reg = 0x0078,
66 .tolerance_regs = 0x0050,
67 .names = { "I", "J", "K", "L" },
68 },
69 {
70 .val_regs = 0x0090,
71 .rdata_reg = 0x007C,
72 .tolerance_regs = 0x00A8,
73 .names = { "M", "N", "O", "P" },
74 },
75 };
76
77 enum aspeed_sgpio_reg {
78 reg_val,
79 reg_rdata,
80 reg_tolerance,
81 };
82
83 struct aspeed_sgpio_llops {
84 void (*reg_bit_set)(struct aspeed_sgpio_priv *gpio, unsigned int offset,
85 const enum aspeed_sgpio_reg reg, bool val);
86 bool (*reg_bit_get)(struct aspeed_sgpio_priv *gpio, unsigned int offset,
87 const enum aspeed_sgpio_reg reg);
88 };
89
90 #define GPIO_VAL_VALUE 0x00
91
bank_reg(struct aspeed_sgpio_priv * gpio,const struct aspeed_sgpio_bank * bank,const enum aspeed_sgpio_reg reg)92 static void __iomem *bank_reg(struct aspeed_sgpio_priv *gpio,
93 const struct aspeed_sgpio_bank *bank,
94 const enum aspeed_sgpio_reg reg)
95 {
96 switch (reg) {
97 case reg_val:
98 return gpio->base + bank->val_regs + GPIO_VAL_VALUE;
99 case reg_rdata:
100 return gpio->base + bank->rdata_reg;
101 case reg_tolerance:
102 return gpio->base + bank->tolerance_regs;
103 default:
104 /* acturally if code runs to here, it's an error case */
105 BUG();
106 }
107 }
108
109 #define GPIO_BANK(x) ((x) >> 6)
110 #define GPIO_OFFSET(x) ((x) & GENMASK(5, 0))
111 #define GPIO_BIT(x) BIT(GPIO_OFFSET(x) >> 1)
112
to_bank(unsigned int offset)113 static const struct aspeed_sgpio_bank *to_bank(unsigned int offset)
114 {
115 unsigned int bank;
116
117 bank = GPIO_BANK(offset);
118
119 WARN_ON(bank >= ARRAY_SIZE(aspeed_sgpio_banks));
120 return &aspeed_sgpio_banks[bank];
121 }
122
aspeed_sgpio_is_input(unsigned int offset)123 static bool aspeed_sgpio_is_input(unsigned int offset)
124 {
125 return !(offset % 2);
126 }
127
aspeed_sgpio_get_value(struct udevice * dev,unsigned int offset)128 static int aspeed_sgpio_get_value(struct udevice *dev, unsigned int offset)
129 {
130 struct aspeed_sgpio_priv *gpio = dev_get_priv(dev);
131 enum aspeed_sgpio_reg reg;
132
133 reg = aspeed_sgpio_is_input(offset) ? reg_val : reg_rdata;
134
135 return gpio->pdata->llops->reg_bit_get(gpio, offset, reg);
136 }
137
aspeed_sgpio_set_value(struct udevice * dev,unsigned int offset,int value)138 static int aspeed_sgpio_set_value(struct udevice *dev, unsigned int offset,
139 int value)
140 {
141 struct aspeed_sgpio_priv *gpio = dev_get_priv(dev);
142
143 if (aspeed_sgpio_is_input(offset))
144 return -EINVAL;
145
146 gpio->pdata->llops->reg_bit_set(gpio, offset, reg_val, value);
147
148 return 0;
149 }
150
aspeed_sgpio_direction_input(struct udevice * dev,unsigned int offset)151 static int aspeed_sgpio_direction_input(struct udevice *dev,
152 unsigned int offset)
153 {
154 return aspeed_sgpio_is_input(offset) ? 0 : -EINVAL;
155 }
156
aspeed_sgpio_set_flags(struct udevice * dev,unsigned int offset,ulong flags)157 static int aspeed_sgpio_set_flags(struct udevice *dev, unsigned int offset, ulong flags)
158 {
159 int ret = -EOPNOTSUPP;
160
161 if (flags & GPIOD_IS_OUT) {
162 bool value = flags & GPIOD_IS_OUT_ACTIVE;
163
164 ret = aspeed_sgpio_set_value(dev, offset, value);
165 } else if (flags & GPIOD_IS_IN) {
166 ret = aspeed_sgpio_direction_input(dev, offset);
167 }
168 return ret;
169 }
170
aspeed_sgpio_get_function(struct udevice * dev,unsigned int offset)171 static int aspeed_sgpio_get_function(struct udevice *dev, unsigned int offset)
172 {
173 return aspeed_sgpio_is_input(offset) ? GPIOF_INPUT : GPIOF_OUTPUT;
174 }
175
aspeed_g4_reg_bit_set(struct aspeed_sgpio_priv * gpio,unsigned int offset,const enum aspeed_sgpio_reg reg,bool val)176 static void aspeed_g4_reg_bit_set(struct aspeed_sgpio_priv *gpio, unsigned int offset,
177 const enum aspeed_sgpio_reg reg, bool val)
178 {
179 const struct aspeed_sgpio_bank *bank = to_bank(offset);
180 void __iomem *addr = bank_reg(gpio, bank, reg);
181 u32 temp;
182
183 if (reg == reg_val)
184 /* Since this is an output, read the cached value from rdata, then update val. */
185 temp = readl(bank_reg(gpio, bank, reg_rdata));
186 else
187 temp = readl(addr);
188
189 if (val)
190 temp |= GPIO_BIT(offset);
191 else
192 temp &= ~GPIO_BIT(offset);
193
194 writel(temp, addr);
195 }
196
aspeed_g4_reg_bit_get(struct aspeed_sgpio_priv * gpio,unsigned int offset,const enum aspeed_sgpio_reg reg)197 static bool aspeed_g4_reg_bit_get(struct aspeed_sgpio_priv *gpio, unsigned int offset,
198 const enum aspeed_sgpio_reg reg)
199 {
200 const struct aspeed_sgpio_bank *bank = to_bank(offset);
201 void __iomem *addr = bank_reg(gpio, bank, reg);
202
203 return !!(readl(addr) & GPIO_BIT(offset));
204 }
205
206 static const struct aspeed_sgpio_llops aspeed_g4_llops = {
207 .reg_bit_set = aspeed_g4_reg_bit_set,
208 .reg_bit_get = aspeed_g4_reg_bit_get,
209 };
210
211 static const struct dm_gpio_ops aspeed_sgpio_ops = {
212 .get_value = aspeed_sgpio_get_value,
213 .set_value = aspeed_sgpio_set_value,
214 .get_function = aspeed_sgpio_get_function,
215 .set_flags = aspeed_sgpio_set_flags,
216 };
217
aspeed_sgpio_probe(struct udevice * dev)218 static int aspeed_sgpio_probe(struct udevice *dev)
219 {
220 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
221 struct aspeed_sgpio_priv *priv = dev_get_priv(dev);
222 u32 sgpio_freq, sgpio_clk_div, nr_gpios, gpio_cnt_regval, pin_mask;
223 ulong apb_freq;
224 int ret;
225
226 priv->base = devfdt_get_addr_ptr(dev);
227 if (IS_ERR(priv->base))
228 return PTR_ERR(priv->base);
229
230 priv->pdata = (const struct aspeed_sgpio_pdata *)dev_get_driver_data(dev);
231 if (!priv->pdata)
232 return -EINVAL;
233
234 pin_mask = priv->pdata->pin_mask;
235
236 ret = ofnode_read_u32(dev_ofnode(dev), "ngpios", &nr_gpios);
237 if (ret < 0) {
238 dev_err(dev, "Could not read ngpios property\n");
239 return -EINVAL;
240 } else if (nr_gpios % 8) {
241 dev_err(dev, "Number of GPIOs not multiple of 8: %d\n",
242 nr_gpios);
243 return -EINVAL;
244 }
245
246 ret = ofnode_read_u32(dev_ofnode(dev), "bus-frequency", &sgpio_freq);
247 if (ret < 0) {
248 dev_err(dev, "Could not read bus-frequency property\n");
249 return -EINVAL;
250 }
251
252 ret = clk_get_by_index(dev, 0, &priv->pclk);
253 if (ret < 0) {
254 dev_err(dev, "get clock failed\n");
255 return ret;
256 }
257
258 apb_freq = clk_get_rate(&priv->pclk);
259
260 /*
261 * From the datasheet,
262 * SGPIO period = 1/PCLK * 2 * (GPIO254[31:16] + 1)
263 * period = 2 * (GPIO254[31:16] + 1) / PCLK
264 * frequency = 1 / (2 * (GPIO254[31:16] + 1) / PCLK)
265 * frequency = PCLK / (2 * (GPIO254[31:16] + 1))
266 * frequency * 2 * (GPIO254[31:16] + 1) = PCLK
267 * GPIO254[31:16] = PCLK / (frequency * 2) - 1
268 */
269 if (sgpio_freq == 0)
270 return -EINVAL;
271
272 sgpio_clk_div = (apb_freq / (sgpio_freq * 2)) - 1;
273
274 if (sgpio_clk_div > (1 << 16) - 1)
275 return -EINVAL;
276
277 gpio_cnt_regval = ((nr_gpios / 8) << ASPEED_SGPIO_PINS_SHIFT) & pin_mask;
278 writel(FIELD_PREP(ASPEED_SGPIO_CLK_DIV_MASK, sgpio_clk_div) | gpio_cnt_regval |
279 ASPEED_SGPIO_ENABLE, priv->base + ASPEED_SGPIO_CTRL);
280
281 uc_priv->bank_name = dev->name;
282 uc_priv->gpio_count = nr_gpios * 2;
283
284 return 0;
285 }
286
287 static const struct aspeed_sgpio_pdata ast2400_sgpio_pdata = {
288 .pin_mask = GENMASK(9, 6),
289 .llops = &aspeed_g4_llops,
290 };
291
292 static const struct aspeed_sgpio_pdata ast2600_sgpiom_pdata = {
293 .pin_mask = GENMASK(10, 6),
294 .llops = &aspeed_g4_llops,
295 };
296
297 static const struct udevice_id aspeed_sgpio_ids[] = {
298 { .compatible = "aspeed,ast2400-sgpio", .data = (ulong)&ast2400_sgpio_pdata, },
299 { .compatible = "aspeed,ast2500-sgpio", .data = (ulong)&ast2400_sgpio_pdata, },
300 { .compatible = "aspeed,ast2600-sgpiom", .data = (ulong)&ast2600_sgpiom_pdata, },
301 };
302
303 U_BOOT_DRIVER(sgpio_aspeed) = {
304 .name = "sgpio-aspeed",
305 .id = UCLASS_GPIO,
306 .of_match = aspeed_sgpio_ids,
307 .ops = &aspeed_sgpio_ops,
308 .probe = aspeed_sgpio_probe,
309 .priv_auto = sizeof(struct aspeed_sgpio_priv),
310 };
311