1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2016-2017 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5 */
6
7 #include <dm.h>
8 #include <linux/bitops.h>
9 #include <linux/io.h>
10 #include <linux/sizes.h>
11 #include <linux/errno.h>
12 #include <asm/global_data.h>
13 #include <asm/gpio.h>
14 #include <dt-bindings/gpio/uniphier-gpio.h>
15
16 #define UNIPHIER_GPIO_PORT_DATA 0x0 /* data */
17 #define UNIPHIER_GPIO_PORT_DIR 0x4 /* direction (1:in, 0:out) */
18 #define UNIPHIER_GPIO_IRQ_EN 0x90 /* irq enable */
19
20 struct uniphier_gpio_priv {
21 void __iomem *regs;
22 };
23
uniphier_gpio_bank_to_reg(unsigned int bank)24 static unsigned int uniphier_gpio_bank_to_reg(unsigned int bank)
25 {
26 unsigned int reg;
27
28 reg = (bank + 1) * 8;
29
30 /*
31 * Unfortunately, the GPIO port registers are not contiguous because
32 * offset 0x90-0x9f is used for IRQ. Add 0x10 when crossing the region.
33 */
34 if (reg >= UNIPHIER_GPIO_IRQ_EN)
35 reg += 0x10;
36
37 return reg;
38 }
39
uniphier_gpio_get_bank_and_mask(unsigned int offset,unsigned int * bank,u32 * mask)40 static void uniphier_gpio_get_bank_and_mask(unsigned int offset,
41 unsigned int *bank, u32 *mask)
42 {
43 *bank = offset / UNIPHIER_GPIO_LINES_PER_BANK;
44 *mask = BIT(offset % UNIPHIER_GPIO_LINES_PER_BANK);
45 }
46
uniphier_gpio_reg_update(struct uniphier_gpio_priv * priv,unsigned int reg,u32 mask,u32 val)47 static void uniphier_gpio_reg_update(struct uniphier_gpio_priv *priv,
48 unsigned int reg, u32 mask, u32 val)
49 {
50 u32 tmp;
51
52 tmp = readl(priv->regs + reg);
53 tmp &= ~mask;
54 tmp |= mask & val;
55 writel(tmp, priv->regs + reg);
56 }
57
uniphier_gpio_bank_write(struct udevice * dev,unsigned int bank,unsigned int reg,u32 mask,u32 val)58 static void uniphier_gpio_bank_write(struct udevice *dev, unsigned int bank,
59 unsigned int reg, u32 mask, u32 val)
60 {
61 struct uniphier_gpio_priv *priv = dev_get_priv(dev);
62
63 if (!mask)
64 return;
65
66 uniphier_gpio_reg_update(priv, uniphier_gpio_bank_to_reg(bank) + reg,
67 mask, val);
68 }
69
uniphier_gpio_offset_write(struct udevice * dev,unsigned int offset,unsigned int reg,int val)70 static void uniphier_gpio_offset_write(struct udevice *dev, unsigned int offset,
71 unsigned int reg, int val)
72 {
73 unsigned int bank;
74 u32 mask;
75
76 uniphier_gpio_get_bank_and_mask(offset, &bank, &mask);
77
78 uniphier_gpio_bank_write(dev, bank, reg, mask, val ? mask : 0);
79 }
80
uniphier_gpio_offset_read(struct udevice * dev,unsigned int offset,unsigned int reg)81 static int uniphier_gpio_offset_read(struct udevice *dev,
82 unsigned int offset, unsigned int reg)
83 {
84 struct uniphier_gpio_priv *priv = dev_get_priv(dev);
85 unsigned int bank, reg_offset;
86 u32 mask;
87
88 uniphier_gpio_get_bank_and_mask(offset, &bank, &mask);
89 reg_offset = uniphier_gpio_bank_to_reg(bank) + reg;
90
91 return !!(readl(priv->regs + reg_offset) & mask);
92 }
93
uniphier_gpio_get_function(struct udevice * dev,unsigned int offset)94 static int uniphier_gpio_get_function(struct udevice *dev, unsigned int offset)
95 {
96 return uniphier_gpio_offset_read(dev, offset, UNIPHIER_GPIO_PORT_DIR) ?
97 GPIOF_INPUT : GPIOF_OUTPUT;
98 }
99
uniphier_gpio_direction_input(struct udevice * dev,unsigned int offset)100 static int uniphier_gpio_direction_input(struct udevice *dev,
101 unsigned int offset)
102 {
103 uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_PORT_DIR, 1);
104
105 return 0;
106 }
107
uniphier_gpio_direction_output(struct udevice * dev,unsigned int offset,int value)108 static int uniphier_gpio_direction_output(struct udevice *dev,
109 unsigned int offset, int value)
110 {
111 uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_PORT_DATA, value);
112 uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_PORT_DIR, 0);
113
114 return 0;
115 }
116
uniphier_gpio_get_value(struct udevice * dev,unsigned int offset)117 static int uniphier_gpio_get_value(struct udevice *dev, unsigned int offset)
118 {
119 return uniphier_gpio_offset_read(dev, offset, UNIPHIER_GPIO_PORT_DATA);
120 }
121
uniphier_gpio_set_value(struct udevice * dev,unsigned int offset,int value)122 static int uniphier_gpio_set_value(struct udevice *dev,
123 unsigned int offset, int value)
124 {
125 uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_PORT_DATA, value);
126
127 return 0;
128 }
129
130 static const struct dm_gpio_ops uniphier_gpio_ops = {
131 .direction_input = uniphier_gpio_direction_input,
132 .direction_output = uniphier_gpio_direction_output,
133 .get_value = uniphier_gpio_get_value,
134 .set_value = uniphier_gpio_set_value,
135 .get_function = uniphier_gpio_get_function,
136 };
137
uniphier_gpio_probe(struct udevice * dev)138 static int uniphier_gpio_probe(struct udevice *dev)
139 {
140 struct uniphier_gpio_priv *priv = dev_get_priv(dev);
141 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
142 fdt_addr_t addr;
143
144 addr = dev_read_addr(dev);
145 if (addr == FDT_ADDR_T_NONE)
146 return -EINVAL;
147
148 priv->regs = devm_ioremap(dev, addr, SZ_512);
149 if (!priv->regs)
150 return -ENOMEM;
151
152 uc_priv->gpio_count = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
153 "ngpios", 0);
154
155 return 0;
156 }
157
158 static const struct udevice_id uniphier_gpio_match[] = {
159 { .compatible = "socionext,uniphier-gpio" },
160 { /* sentinel */ }
161 };
162
163 U_BOOT_DRIVER(uniphier_gpio) = {
164 .name = "uniphier-gpio",
165 .id = UCLASS_GPIO,
166 .of_match = uniphier_gpio_match,
167 .probe = uniphier_gpio_probe,
168 .priv_auto = sizeof(struct uniphier_gpio_priv),
169 .ops = &uniphier_gpio_ops,
170 };
171