1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2019 Google LLC
4 */
5
6 #define LOG_CATEGORY UCLASS_GPIO
7
8 #include <dm.h>
9 #include <errno.h>
10 #include <fdtdec.h>
11 #include <log.h>
12 #include <p2sb.h>
13 #include <pch.h>
14 #include <pci.h>
15 #include <syscon.h>
16 #include <acpi/acpi_device.h>
17 #include <asm/cpu.h>
18 #include <asm/gpio.h>
19 #include <asm/intel_pinctrl.h>
20 #include <asm/intel_pinctrl_defs.h>
21 #include <asm/io.h>
22 #include <asm/pci.h>
23 #include <asm/arch/gpio.h>
24 #include <dm/acpi.h>
25 #include <dm/device-internal.h>
26 #include <dt-bindings/gpio/x86-gpio.h>
27
intel_gpio_get_value(struct udevice * dev,uint offset)28 static int intel_gpio_get_value(struct udevice *dev, uint offset)
29 {
30 struct udevice *pinctrl = dev_get_parent(dev);
31 uint mode, rx_tx;
32 u32 reg;
33
34 reg = intel_pinctrl_get_config_reg(pinctrl, offset);
35 mode = (reg & PAD_CFG0_MODE_MASK) >> PAD_CFG0_MODE_SHIFT;
36 if (!mode) {
37 rx_tx = reg & (PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE);
38 if (rx_tx == PAD_CFG0_TX_DISABLE)
39 return reg & PAD_CFG0_RX_STATE ? 1 : 0;
40 else if (rx_tx == PAD_CFG0_RX_DISABLE)
41 return reg & PAD_CFG0_TX_STATE ? 1 : 0;
42 }
43
44 return 0;
45 }
46
intel_gpio_set_value(struct udevice * dev,unsigned int offset,int value)47 static int intel_gpio_set_value(struct udevice *dev, unsigned int offset,
48 int value)
49 {
50 struct udevice *pinctrl = dev_get_parent(dev);
51 uint config_offset;
52
53 config_offset = intel_pinctrl_get_config_reg_offset(pinctrl, offset);
54
55 pcr_clrsetbits32(pinctrl, config_offset, PAD_CFG0_TX_STATE,
56 value ? PAD_CFG0_TX_STATE : 0);
57
58 return 0;
59 }
60
intel_gpio_get_function(struct udevice * dev,uint offset)61 static int intel_gpio_get_function(struct udevice *dev, uint offset)
62 {
63 struct udevice *pinctrl = dev_get_parent(dev);
64 uint mode, rx_tx;
65 u32 reg;
66
67 reg = intel_pinctrl_get_config_reg(pinctrl, offset);
68 mode = (reg & PAD_CFG0_MODE_MASK) >> PAD_CFG0_MODE_SHIFT;
69 if (!mode) {
70 rx_tx = reg & (PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE);
71 if (rx_tx == PAD_CFG0_TX_DISABLE)
72 return GPIOF_INPUT;
73 else if (rx_tx == PAD_CFG0_RX_DISABLE)
74 return GPIOF_OUTPUT;
75 }
76
77 return GPIOF_FUNC;
78 }
79
intel_gpio_xlate(struct udevice * orig_dev,struct gpio_desc * desc,struct ofnode_phandle_args * args)80 static int intel_gpio_xlate(struct udevice *orig_dev, struct gpio_desc *desc,
81 struct ofnode_phandle_args *args)
82 {
83 struct udevice *pinctrl, *dev;
84 int gpio, ret;
85
86 /*
87 * GPIO numbers are global in the device tree so it doesn't matter
88 * which @orig_dev is used
89 */
90 gpio = args->args[0];
91 ret = intel_pinctrl_get_pad(gpio, &pinctrl, &desc->offset);
92 if (ret)
93 return log_msg_ret("bad", ret);
94 device_find_first_child(pinctrl, &dev);
95 if (!dev)
96 return log_msg_ret("no child", -ENOENT);
97 desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
98 desc->dev = dev;
99
100 /*
101 * Handle the case where the wrong GPIO device was provided, since this
102 * will not have been probed by the GPIO uclass before calling here
103 * (see gpio_request_tail()).
104 */
105 if (orig_dev != dev) {
106 ret = device_probe(dev);
107 if (ret)
108 return log_msg_ret("probe", ret);
109 }
110
111 return 0;
112 }
113
intel_gpio_set_flags(struct udevice * dev,unsigned int offset,ulong flags)114 static int intel_gpio_set_flags(struct udevice *dev, unsigned int offset,
115 ulong flags)
116 {
117 struct udevice *pinctrl = dev_get_parent(dev);
118 u32 bic0 = 0, bic1 = 0;
119 u32 or0, or1;
120 uint config_offset;
121
122 config_offset = intel_pinctrl_get_config_reg_offset(pinctrl, offset);
123
124 if (flags & GPIOD_IS_OUT) {
125 bic0 |= PAD_CFG0_MODE_MASK | PAD_CFG0_RX_STATE |
126 PAD_CFG0_TX_DISABLE;
127 or0 |= PAD_CFG0_MODE_GPIO | PAD_CFG0_RX_DISABLE;
128 } else if (flags & GPIOD_IS_IN) {
129 bic0 |= PAD_CFG0_MODE_MASK | PAD_CFG0_TX_STATE |
130 PAD_CFG0_RX_DISABLE;
131 or0 |= PAD_CFG0_MODE_GPIO | PAD_CFG0_TX_DISABLE;
132 }
133 if (flags & GPIOD_PULL_UP) {
134 bic1 |= PAD_CFG1_PULL_MASK;
135 or1 |= PAD_CFG1_PULL_UP_20K;
136 } else if (flags & GPIOD_PULL_DOWN) {
137 bic1 |= PAD_CFG1_PULL_MASK;
138 or1 |= PAD_CFG1_PULL_DN_20K;
139 }
140
141 pcr_clrsetbits32(pinctrl, PAD_CFG0_OFFSET(config_offset), bic0, or0);
142 pcr_clrsetbits32(pinctrl, PAD_CFG1_OFFSET(config_offset), bic1, or1);
143 log_debug("%s: flags=%lx, offset=%x, config_offset=%x, %x/%x %x/%x\n",
144 dev->name, flags, offset, config_offset, bic0, or0, bic1, or1);
145
146 return 0;
147 }
148
149 #if CONFIG_IS_ENABLED(ACPIGEN)
intel_gpio_get_acpi(const struct gpio_desc * desc,struct acpi_gpio * gpio)150 static int intel_gpio_get_acpi(const struct gpio_desc *desc,
151 struct acpi_gpio *gpio)
152 {
153 struct udevice *pinctrl;
154 int ret;
155
156 if (!dm_gpio_is_valid(desc))
157 return -ENOENT;
158 pinctrl = dev_get_parent(desc->dev);
159
160 memset(gpio, '\0', sizeof(*gpio));
161
162 gpio->type = ACPI_GPIO_TYPE_IO;
163 gpio->pull = ACPI_GPIO_PULL_DEFAULT;
164 gpio->io_restrict = ACPI_GPIO_IO_RESTRICT_OUTPUT;
165 gpio->polarity = ACPI_GPIO_ACTIVE_HIGH;
166 gpio->pin_count = 1;
167 gpio->pins[0] = intel_pinctrl_get_acpi_pin(pinctrl, desc->offset);
168 gpio->pin0_addr = intel_pinctrl_get_config_reg_addr(pinctrl,
169 desc->offset);
170 ret = acpi_get_path(pinctrl, gpio->resource, sizeof(gpio->resource));
171 if (ret)
172 return log_msg_ret("resource", ret);
173
174 return 0;
175 }
176 #endif
177
intel_gpio_probe(struct udevice * dev)178 static int intel_gpio_probe(struct udevice *dev)
179 {
180 return 0;
181 }
182
intel_gpio_of_to_plat(struct udevice * dev)183 static int intel_gpio_of_to_plat(struct udevice *dev)
184 {
185 struct gpio_dev_priv *upriv = dev_get_uclass_priv(dev);
186 struct intel_pinctrl_priv *pinctrl_priv = dev_get_priv(dev->parent);
187 const struct pad_community *comm = pinctrl_priv->comm;
188
189 upriv->gpio_count = comm->last_pad - comm->first_pad + 1;
190 upriv->bank_name = dev->name;
191
192 return 0;
193 }
194
195 static const struct dm_gpio_ops gpio_intel_ops = {
196 .get_value = intel_gpio_get_value,
197 .set_value = intel_gpio_set_value,
198 .get_function = intel_gpio_get_function,
199 .xlate = intel_gpio_xlate,
200 .set_flags = intel_gpio_set_flags,
201 #if CONFIG_IS_ENABLED(ACPIGEN)
202 .get_acpi = intel_gpio_get_acpi,
203 #endif
204 };
205
206 #if CONFIG_IS_ENABLED(OF_REAL)
207 static const struct udevice_id intel_intel_gpio_ids[] = {
208 { .compatible = "intel,gpio" },
209 { }
210 };
211 #endif
212
213 U_BOOT_DRIVER(intel_gpio) = {
214 .name = "intel_gpio",
215 .id = UCLASS_GPIO,
216 .of_match = of_match_ptr(intel_intel_gpio_ids),
217 .ops = &gpio_intel_ops,
218 .of_to_plat = intel_gpio_of_to_plat,
219 .probe = intel_gpio_probe,
220 };
221