1#
2# I2C subsystem configuration
3#
4
5menuconfig I2C
6	bool "I2C support"
7	default y
8	help
9	  Note:
10	  This is a stand-in for an option to enable I2C support. In fact this
11	  simply enables building of the I2C directory for U-Boot. The actual
12	  I2C feature is enabled by DM_I2C (for driver model) and
13	  the #define CONFIG_SYS_I2C_LEGACY (for the legacy I2C stack).
14
15	  So at present there is no need to ever disable this option.
16
17	  Eventually it will:
18
19	  Enable support for the I2C (Inter-Integrated Circuit) bus in U-Boot.
20	  I2C works with a clock and data line which can be driven by a
21	  one or more masters or slaves. It is a fairly complex bus but is
22	  widely used as it only needs two lines for communication. Speeds of
23	  400kbps are typical but up to 3.4Mbps is supported by some
24	  hardware. Enable this option to build the drivers in drivers/i2c as
25	  part of a U-Boot build.
26
27if I2C
28
29config DM_I2C
30	bool "Enable Driver Model for I2C drivers"
31	depends on DM
32	help
33	  Enable driver model for I2C. The I2C uclass interface: probe, read,
34	  write and speed, is implemented with the bus drivers operations,
35	  which provide methods for bus setting and data transfer. Each chip
36	  device (bus child) info is kept as parent plat. The interface
37	  is defined in include/i2c.h.
38
39config SPL_DM_I2C
40	bool "Enable Driver Model for I2C drivers in SPL"
41	depends on SPL_DM && DM_I2C
42	default y
43	help
44	  Enable driver model for I2C. The I2C uclass interface: probe, read,
45	  write and speed, is implemented with the bus drivers operations,
46	  which provide methods for bus setting and data transfer. Each chip
47	  device (bus child) info is kept as parent platdata. The interface
48	  is defined in include/i2c.h.
49
50config TPL_DM_I2C
51	bool "Enable Driver Model for I2C drivers in TPL"
52	depends on TPL_DM && DM_I2C
53	help
54	  Enable driver model for I2C. The I2C uclass interface: probe, read,
55	  write and speed, is implemented with the bus drivers operations,
56	  which provide methods for bus setting and data transfer. Each chip
57	  device (bus child) info is kept as parent platdata. The interface
58	  is defined in include/i2c.h.
59
60config VPL_DM_I2C
61	bool "Enable Driver Model for I2C drivers in VPL"
62	depends on VPL_DM && DM_I2C
63	default y
64	help
65	  Enable driver model for I2C. The I2C uclass interface: probe, read,
66	  write and speed, is implemented with the bus drivers operations,
67	  which provide methods for bus setting and data transfer. Each chip
68	  device (bus child) info is kept as parent platdata. The interface
69	  is defined in include/i2c.h.
70
71config SYS_I2C_LEGACY
72	bool "Enable legacy I2C subsystem and drivers"
73	depends on !DM_I2C
74	help
75	  Enable the legacy I2C subsystem and drivers.  While this is
76	  deprecated in U-Boot itself, this can be useful in some situations
77	  in SPL or TPL.
78
79config SPL_SYS_I2C_LEGACY
80	bool "Enable legacy I2C subsystem and drivers in SPL"
81	depends on SUPPORT_SPL && !SPL_DM_I2C
82	help
83	  Enable the legacy I2C subsystem and drivers in SPL.  This is useful
84	  in some size constrained situations.
85
86config TPL_SYS_I2C_LEGACY
87	bool "Enable legacy I2C subsystem and drivers in TPL"
88	depends on SUPPORT_TPL && !SPL_DM_I2C
89	help
90	  Enable the legacy I2C subsystem and drivers in TPL.  This is useful
91	  in some size constrained situations.
92
93config SYS_I2C_EARLY_INIT
94	bool "Enable legacy I2C subsystem early in boot"
95	depends on BOARD_EARLY_INIT_F && SPL_SYS_I2C_LEGACY && SYS_I2C_MXC
96	help
97	  Add the function prototype for i2c_early_init_f which is called in
98	  board_early_init_f.
99
100config I2C_CROS_EC_TUNNEL
101	tristate "Chrome OS EC tunnel I2C bus"
102	depends on CROS_EC
103	help
104	  This provides an I2C bus that will tunnel i2c commands through to
105	  the other side of the Chrome OS EC to the I2C bus connected there.
106	  This will work whatever the interface used to talk to the EC (SPI,
107	  I2C or LPC). Some Chromebooks use this when the hardware design
108	  does not allow direct access to the main PMIC from the AP.
109
110config I2C_CROS_EC_LDO
111	bool "Provide access to LDOs on the Chrome OS EC"
112	depends on CROS_EC
113	---help---
114	On many Chromebooks the main PMIC is inaccessible to the AP. This is
115	often dealt with by using an I2C pass-through interface provided by
116	the EC. On some unfortunate models (e.g. Spring) the pass-through
117	is not available, and an LDO message is available instead. This
118	option enables a driver which provides very basic access to those
119	regulators, via the EC. We implement this as an I2C bus	which
120	emulates just the TPS65090 messages we know about. This is done to
121	avoid duplicating the logic in the TPS65090 regulator driver for
122	enabling/disabling an LDO.
123
124config I2C_SET_DEFAULT_BUS_NUM
125	bool "Set default I2C bus number"
126	depends on DM_I2C
127	help
128	  Set default number of I2C bus to be accessed. This option provides
129	  behaviour similar to old (i.e. pre DM) I2C bus driver.
130
131config I2C_DEFAULT_BUS_NUMBER
132	hex "I2C default bus number"
133	depends on I2C_SET_DEFAULT_BUS_NUM
134	default 0x0
135	help
136	  Number of default I2C bus to use
137
138config DM_I2C_GPIO
139	bool "Enable Driver Model for software emulated I2C bus driver"
140	depends on DM_I2C && DM_GPIO
141	help
142	  Enable the i2c bus driver emulation by using the GPIOs. The bus GPIO
143	  configuration is given by the device tree. Kernel-style device tree
144	  bindings are supported.
145	  Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
146
147config SPL_DM_I2C_GPIO
148	bool "Enable Driver Model for software emulated I2C bus driver in SPL"
149	depends on SPL_DM && DM_I2C_GPIO && SPL_DM_GPIO && SPL_GPIO
150	default y
151	help
152	  Enable the i2c bus driver emulation by using the GPIOs. The bus GPIO
153	  configuration is given by the device tree. Kernel-style device tree
154	  bindings are supported.
155	  Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
156
157config SYS_I2C_ADI
158	bool "ADI I2C driver"
159	depends on DM_I2C && ARCH_SC5XX
160	help
161	  Add support for the ADI (Analog Devices) I2C driver as used
162	  in SC57X, SC58X, SC59X, SC59X_64.
163
164config SYS_I2C_AT91
165	bool "Atmel I2C driver"
166	depends on DM_I2C && ARCH_AT91
167	help
168	  Add support for the Atmel I2C driver. A serious problem is that there
169	  is no documented way to issue repeated START conditions for more than
170	  two messages, as needed to support combined I2C messages. Use the
171	  i2c-gpio driver unless your system can cope with this limitation.
172	  Binding info: doc/device-tree-bindings/i2c/i2c-at91.txt
173
174config SYS_I2C_IPROC
175	bool "Broadcom I2C driver"
176	depends on DM_I2C
177	help
178	  Broadcom I2C driver.
179	  Add support for Broadcom I2C driver.
180	  Say yes here to to enable the Broadco I2C driver.
181
182config SYS_I2C_FSL
183       bool "Freescale I2C bus driver"
184       depends on M68K || PPC
185       help
186	  Add support for Freescale I2C busses as used on MPC8240, MPC8245, and
187	  MPC85xx processors.
188
189if SYS_I2C_FSL && (SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY)
190config SYS_FSL_I2C_OFFSET
191	hex "Offset from the IMMR of the address of the first I2C controller"
192
193config SYS_FSL_HAS_I2C2_OFFSET
194	bool "Support a second I2C controller"
195
196config SYS_FSL_I2C2_OFFSET
197	hex "Offset from the IMMR of the address of the second I2C controller"
198	depends on SYS_FSL_HAS_I2C2_OFFSET
199
200config SYS_FSL_HAS_I2C3_OFFSET
201	bool "Support a third I2C controller"
202
203config SYS_FSL_I2C3_OFFSET
204	hex "Offset from the IMMR of the address of the third I2C controller"
205	depends on SYS_FSL_HAS_I2C3_OFFSET
206
207config SYS_FSL_HAS_I2C4_OFFSET
208	bool "Support a fourth I2C controller"
209
210config SYS_FSL_I2C4_OFFSET
211	hex "Offset from the IMMR of the address of the fourth I2C controller"
212	depends on SYS_FSL_HAS_I2C4_OFFSET
213endif
214
215config SYS_I2C_CADENCE
216	tristate "Cadence I2C Controller"
217	depends on DM_I2C
218	help
219	  Say yes here to select Cadence I2C Host Controller. This controller is
220	  e.g. used by Xilinx Zynq.
221
222config SYS_I2C_CA
223	tristate "Cortina-Access I2C Controller"
224	depends on DM_I2C && CORTINA_PLATFORM
225	help
226	  Add support for the Cortina Access I2C host controller.
227	  Say yes here to select Cortina-Access I2C Host Controller.
228
229config SYS_I2C_DAVINCI
230	bool "Davinci I2C Controller"
231	depends on (ARCH_KEYSTONE || ARCH_DAVINCI)
232	help
233	  Say yes here to add support for Davinci and Keystone I2C controller
234
235config SYS_I2C_DW
236	bool "Designware I2C Controller"
237	help
238	  Say yes here to select the Designware I2C Host Controller. This
239	  controller is used in various SoCs, e.g. the ST SPEAr, Altera
240	  SoCFPGA, Synopsys ARC700 and some Intel x86 SoCs.
241
242config SYS_I2C_DW_PCI
243	bool "Designware PCI I2C Controller"
244	depends on SYS_I2C_DW && PCI && ACPIGEN && X86
245	default y
246	help
247	  Say yes here to select the Designware PCI I2C Host Controller.
248	  This PCI I2C controller is the base on Desigware I2C host
249	  controller.
250
251config SYS_I2C_AST2600
252    bool "AST2600 I2C Controller"
253    depends on DM_I2C && ARCH_ASPEED
254    help
255      Say yes here to select AST2600 I2C Host Controller. The driver
256      support AST2600 I2C new mode register. This I2C controller supports:
257      _Standard-mode (up to 100 kHz)
258      _Fast-mode (up to 400 kHz)
259      _Fast-mode Plus (up to 1 MHz)
260
261config SYS_I2C_ASPEED
262	bool "Aspeed I2C Controller"
263	depends on DM_I2C && ARCH_ASPEED
264	help
265	  Say yes here to select Aspeed I2C Host Controller. The driver
266	  supports AST2500 and AST2400 controllers, but is very limited.
267	  Only single master mode is supported and only byte-by-byte
268	  synchronous reads and writes are supported, no Pool Buffers or DMA.
269
270config SYS_I2C_INTEL
271	bool "Intel I2C/SMBUS driver"
272	depends on DM_I2C
273	help
274	  Add support for the Intel SMBUS driver. So far this driver is just
275	  a stub which perhaps some basic init. There is no implementation of
276	  the I2C API meaning that any I2C operations will immediately fail
277	  for now.
278
279config SYS_I2C_IMX_LPI2C
280	bool "NXP i.MX LPI2C driver"
281	depends on MACH_IMX
282	help
283	  Add support for the NXP i.MX LPI2C driver.
284
285config SYS_I2C_LPC32XX
286	bool "LPC32XX I2C driver"
287	depends on ARCH_LPC32XX
288	help
289	  Enable support for the LPC32xx I2C driver.
290
291config SYS_I2C_MESON
292	bool "Amlogic Meson I2C driver"
293	depends on DM_I2C && ARCH_MESON
294	help
295	  Add support for the I2C controller available in Amlogic Meson
296	  SoCs. The controller supports programmable bus speed including
297	  standard (100kbits/s) and fast (400kbit/s) speed and allows the
298	  software to define a flexible format of the bit streams. It has an
299	  internal buffer holding up to 8 bytes for transfers and supports
300	  both 7-bit and 10-bit addresses.
301
302config SYS_I2C_MTK
303	bool "MediaTek I2C driver"
304	help
305	  This selects the MediaTek Integrated Inter Circuit bus driver.
306	  The I2C bus adapter is the base for some other I2C client,
307	  eg: touch, sensors.
308	  If you want to use MediaTek I2C interface, say Y here.
309	  If unsure, say N.
310
311config SYS_I2C_MICROCHIP
312	bool "Microchip I2C driver"
313	help
314	  Add support for the Microchip I2C driver. This is operating on
315	  standard mode up to 100 kbits/s and fast mode up to 400 kbits/s.
316
317config SYS_I2C_MXC
318	bool "NXP MXC I2C driver"
319	depends on ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3 || MACH_IMX
320	help
321	  Add support for the NXP I2C driver. This supports up to four bus
322	  channels and operating on standard mode up to 100 kbits/s and fast
323	  mode up to 400 kbits/s.
324
325if SYS_I2C_MXC && (SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY)
326config SYS_I2C_MXC_I2C1
327	bool "NXP MXC I2C1"
328	help
329	 Add support for NXP MXC I2C Controller 1.
330	 Required for SoCs which have I2C MXC controller 1 eg LS1088A, LS2080A
331
332config SYS_I2C_MXC_I2C2
333	bool "NXP MXC I2C2"
334	help
335	 Add support for NXP MXC I2C Controller 2.
336	 Required for SoCs which have I2C MXC controller 2 eg LS1088A, LS2080A
337
338config SYS_I2C_MXC_I2C3
339	bool "NXP MXC I2C3"
340	help
341	 Add support for NXP MXC I2C Controller 3.
342	 Required for SoCs which have I2C MXC controller 3 eg LS1088A, LS2080A
343
344config SYS_I2C_MXC_I2C4
345	bool "NXP MXC I2C4"
346	help
347	 Add support for NXP MXC I2C Controller 4.
348	 Required for SoCs which have I2C MXC controller 4 eg LS1088A, LS2080A
349
350config SYS_I2C_MXC_I2C5
351	bool "NXP MXC I2C5"
352	help
353	 Add support for NXP MXC I2C Controller 5.
354	 Required for SoCs which have I2C MXC controller 5 eg LX2160A
355
356config SYS_I2C_MXC_I2C6
357	bool "NXP MXC I2C6"
358	help
359	 Add support for NXP MXC I2C Controller 6.
360	 Required for SoCs which have I2C MXC controller 6 eg LX2160A
361
362config SYS_I2C_MXC_I2C7
363	bool "NXP MXC I2C7"
364	help
365	 Add support for NXP MXC I2C Controller 7.
366	 Required for SoCs which have I2C MXC controller 7 eg LX2160A
367
368config SYS_I2C_MXC_I2C8
369	bool "NXP MXC I2C8"
370	help
371	 Add support for NXP MXC I2C Controller 8.
372	 Required for SoCs which have I2C MXC controller 8 eg LX2160A
373endif
374
375if SYS_I2C_MXC_I2C1
376config SYS_MXC_I2C1_SPEED
377	int "I2C Channel 1 speed"
378	default 40000000 if TARGET_LS2080A_EMU
379	default 100000
380	help
381	 MXC I2C Channel 1 speed
382
383config SYS_MXC_I2C1_SLAVE
384	hex "I2C1 Slave"
385	default 0x0
386	help
387	 MXC I2C1 Slave
388endif
389
390if SYS_I2C_MXC_I2C2
391config SYS_MXC_I2C2_SPEED
392	int "I2C Channel 2 speed"
393	default 40000000 if TARGET_LS2080A_EMU
394	default 100000
395	help
396	 MXC I2C Channel 2 speed
397
398config SYS_MXC_I2C2_SLAVE
399	hex "I2C2 Slave"
400	default 0x0
401	help
402	 MXC I2C2 Slave
403endif
404
405if SYS_I2C_MXC_I2C3
406config SYS_MXC_I2C3_SPEED
407	int "I2C Channel 3 speed"
408	default 100000
409	help
410	 MXC I2C Channel 3 speed
411
412config SYS_MXC_I2C3_SLAVE
413	hex "I2C3 Slave"
414	default 0x0
415	help
416	 MXC I2C3 Slave
417endif
418
419if SYS_I2C_MXC_I2C4
420config SYS_MXC_I2C4_SPEED
421	int "I2C Channel 4 speed"
422	default 100000
423	help
424	 MXC I2C Channel 4 speed
425
426config SYS_MXC_I2C4_SLAVE
427	hex "I2C4 Slave"
428	default 0x0
429	help
430	 MXC I2C4 Slave
431endif
432
433if SYS_I2C_MXC_I2C5
434config SYS_MXC_I2C5_SPEED
435	int "I2C Channel 5 speed"
436	default 100000
437	help
438	 MXC I2C Channel 5 speed
439
440config SYS_MXC_I2C5_SLAVE
441	hex "I2C5 Slave"
442	default 0x0
443	help
444	 MXC I2C5 Slave
445endif
446
447if SYS_I2C_MXC_I2C6
448config SYS_MXC_I2C6_SPEED
449	int "I2C Channel 6 speed"
450	default 100000
451	help
452	 MXC I2C Channel 6 speed
453
454config SYS_MXC_I2C6_SLAVE
455	hex "I2C6 Slave"
456	default 0x0
457	help
458	 MXC I2C6 Slave
459endif
460
461if SYS_I2C_MXC_I2C7
462config SYS_MXC_I2C7_SPEED
463	int "I2C Channel 7 speed"
464	default 100000
465	help
466	 MXC I2C Channel 7 speed
467
468config SYS_MXC_I2C7_SLAVE
469	hex "I2C7 Slave"
470	default 0x0
471	help
472	 MXC I2C7 Slave
473endif
474
475if SYS_I2C_MXC_I2C8
476config SYS_MXC_I2C8_SPEED
477	int "I2C Channel 8 speed"
478	default 100000
479	help
480	 MXC I2C Channel 8 speed
481
482config SYS_MXC_I2C8_SLAVE
483	hex "I2C8 Slave"
484	default 0x0
485	help
486	 MXC I2C8 Slave
487endif
488
489config SYS_I2C_NEXELL
490	bool "Nexell I2C driver"
491	depends on DM_I2C && ARCH_NEXELL
492	help
493	  Add support for the Nexell I2C driver. This is used with various
494	  Nexell parts such as S5Pxx18 series SoCs. All chips
495	  have several I2C ports and all are provided, controlled by the
496	  device tree.
497
498config SYS_I2C_NPCM
499	bool "Nuvoton NPCM I2C driver"
500	depends on ARCH_NPCM
501	help
502	  Support for Nuvoton I2C controller driver.
503
504config SYS_I2C_OCORES
505	bool "ocores I2C driver"
506	depends on DM_I2C
507	help
508	  Add support for ocores I2C controller. For details see
509	  https://opencores.org/projects/i2c
510
511config SYS_I2C_OMAP24XX
512	bool "TI OMAP2+ I2C driver"
513	depends on ARCH_OMAP2PLUS || ARCH_K3
514	help
515	  Add support for the OMAP2+ I2C driver.
516
517config SYS_I2C_OMAP24XX_REPEATED_START
518	bool "Enable I2C repeated start"
519	depends on SYS_I2C_OMAP24XX
520	default y if ARCH_K3
521	help
522	  Enable support for repeated start. Updates driver defaults to not
523	  send a Stop condition and issue Repeated Start (Sr) for subsequent
524	  i2c msgs.
525
526config SYS_I2C_RCAR_I2C
527	bool "Renesas R-Car I2C driver"
528	depends on (RCAR_GEN2 || RCAR_64) && DM_I2C
529	help
530	  Support for Renesas R-Car I2C controller.
531
532config SYS_I2C_RCAR_IIC
533	bool "Renesas R-Car Gen3 IIC driver"
534	depends on (RCAR_GEN2 || RCAR_GEN3) && DM_I2C
535	help
536	  Support for Renesas R-Car Gen3 IIC controller.
537
538config SYS_I2C_ROCKCHIP
539	bool "Rockchip I2C driver"
540	depends on DM_I2C && ARCH_ROCKCHIP
541	help
542	  Add support for the Rockchip I2C driver. This is used with various
543	  Rockchip parts such as RK3126, RK3128, RK3036 and RK3288. All chips
544	  have several I2C ports and all are provided, controlled by the
545	  device tree.
546
547config SYS_I2C_RZ_RIIC
548	bool "Renesas RZ/G2L RIIC driver"
549	depends on RZG2L && DM_I2C
550	help
551	  Support for the I2C controller (RIIC) on the Renesas RZ/G2L SoC
552	  family.
553
554config SYS_I2C_SANDBOX
555	bool "Sandbox I2C driver"
556	depends on SANDBOX && DM_I2C
557	default y
558	help
559	  Enable I2C support for sandbox. This is an emulation of a real I2C
560	  bus. Devices can be attached to the bus using the device tree
561	  which specifies the driver to use.  See sandbox.dts as an example.
562
563config SPL_SYS_I2C_SANDBOX
564	bool "Sandbox I2C driver (SPL)"
565	depends on SPL && SANDBOX && DM_I2C
566	default y
567	help
568	  Enable I2C support for sandbox. This is an emulation of a real I2C
569	  bus. Devices can be attached to the bus using the device tree
570	  which specifies the driver to use.  See sandbox.dts as an example.
571
572config SYS_I2C_SH
573	bool "Legacy SuperH I2C interface"
574	depends on ARCH_RENESAS && SYS_I2C_LEGACY
575	help
576	  Enable the legacy SuperH I2C interface.
577
578if SYS_I2C_SH
579config SYS_I2C_SH_NUM_CONTROLLERS
580	int
581	default 5
582
583config SYS_I2C_SH_BASE0
584	hex
585	default 0xE6820000
586
587config SYS_I2C_SH_BASE1
588	hex
589	default 0xE6822000
590
591config SYS_I2C_SH_BASE2
592	hex
593	default 0xE6824000
594
595config SYS_I2C_SH_BASE3
596	hex
597	default 0xE6826000
598
599config SYS_I2C_SH_BASE4
600	hex
601	default 0xE6828000
602
603config SH_I2C_8BIT
604	bool
605	default y
606
607config SH_I2C_DATA_HIGH
608	int
609	default 4
610
611config SH_I2C_DATA_LOW
612	int
613	default 5
614
615config SH_I2C_CLOCK
616	int
617	default 104000000
618endif
619
620config SYS_I2C_SOFT
621	bool "Legacy software I2C interface"
622	depends on !COMPILE_TEST
623	help
624	  Enable the legacy software defined I2C interface
625
626config SYS_I2C_SOFT_SPEED
627	int "Software I2C bus speed"
628	depends on SYS_I2C_SOFT
629	default 100000
630	help
631	  Speed of the software I2C bus
632
633config SYS_I2C_SOFT_SLAVE
634	hex "Software I2C slave address"
635	depends on SYS_I2C_SOFT
636	default 0xfe
637	help
638	  Slave address of the software I2C bus
639
640config SYS_I2C_OCTEON
641	bool "Octeon II/III/TX/TX2 I2C driver"
642	depends on (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2) && DM_I2C
643	default y
644	help
645	  Add support for the Marvell Octeon I2C driver. This is used with
646	  various Octeon parts such as Octeon II/III and OcteonTX/TX2. All
647	  chips have several I2C ports and all are provided, controlled by
648	  the device tree.
649
650config SYS_I2C_QUP
651	bool "Qualcomm QUP I2C controller"
652	depends on ARCH_SNAPDRAGON
653	help
654	  Support for Qualcomm QUP I2C controller based on Qualcomm Universal
655	  Peripherals (QUP) engine. The QUP engine is an advanced high
656	  performance slave port that provides a common data path (an output
657	  FIFO and an input FIFO) for I2C and SPI interfaces. The I2C/SPI QUP
658	  controller is publicly documented in the Snapdragon 410E (APQ8016E)
659	  Technical Reference Manual, chapter "6.1 Qualcomm Universal
660	  Peripherals Engine (QUP)".
661
662config SYS_I2C_GENI
663	bool "Qualcomm Generic Interface (GENI) I2C controller"
664	depends on ARCH_SNAPDRAGON
665	help
666	  Support for the Qualcomm Generic Interface (GENI) I2C interface.
667	  The Generic Interface (GENI) is a firmware based Qualcomm Universal
668	  Peripherals (QUP) Serial Engine (SE) Wrapper which can support multiple
669	  bus protocols depending on the firmware type loaded at early boot time
670	  based on system configuration.
671
672config SYS_I2C_S3C24X0
673	bool "Samsung I2C driver"
674	depends on DM_I2C
675	help
676	  Support for Samsung I2C controller as Samsung SoCs.
677
678config SYS_I2C_STM32F7
679	bool "STMicroelectronics STM32F7 I2C support"
680	depends on (STM32F7 || STM32H7 || ARCH_STM32MP) && DM_I2C
681	help
682	  Enable this option to add support for STM32 I2C controller
683	  introduced with STM32F7/H7 SoCs. This I2C controller supports :
684	   _ Slave and master modes
685	   _ Multimaster capability
686	   _ Standard-mode (up to 100 kHz)
687	   _ Fast-mode (up to 400 kHz)
688	   _ Fast-mode Plus (up to 1 MHz)
689	   _ 7-bit and 10-bit addressing mode
690	   _ Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask)
691	   _ All 7-bit addresses acknowledge mode
692	   _ General call
693	   _ Programmable setup and hold times
694	   _ Easy to use event management
695	   _ Optional clock stretching
696	   _ Software reset
697
698config SYS_I2C_SUN6I_P2WI
699	bool "Allwinner sun6i P2WI controller"
700	depends on ARCH_SUNXI
701	help
702	  Support for the P2WI (Push/Pull 2 Wire Interface) controller embedded
703	  in the Allwinner A31 and A31s SOCs. This interface is used to connect
704	  to specific devices like the X-Powers AXP221 PMIC.
705
706config SYS_I2C_SUN8I_RSB
707	bool "Allwinner sun8i Reduced Serial Bus controller"
708	depends on ARCH_SUNXI
709	help
710	  Support for Allwinner's Reduced Serial Bus (RSB) controller. This
711	  controller is responsible for communicating with various RSB based
712	  devices, such as X-Powers AXPxxx PMICs and AC100/AC200 CODEC ICs.
713
714config SYS_I2C_SYNQUACER
715	bool "Socionext SynQuacer I2C controller"
716	depends on ARCH_SYNQUACER && DM_I2C
717	help
718	  Support for Socionext Synquacer I2C controller. This I2C controller
719	  will be used for RTC and LS-connector on DeveloperBox.
720
721config SYS_I2C_TEGRA
722	bool "NVIDIA Tegra internal I2C controller"
723	depends on ARCH_TEGRA
724	help
725	  Support for NVIDIA I2C controller available in Tegra SoCs.
726
727config SYS_I2C_UNIPHIER
728	bool "UniPhier I2C driver"
729	depends on ARCH_UNIPHIER && DM_I2C
730	default y
731	help
732	  Support for UniPhier I2C controller driver.  This I2C controller
733	  is used on PH1-LD4, PH1-sLD8 or older UniPhier SoCs.
734
735config SYS_I2C_UNIPHIER_F
736	bool "UniPhier FIFO-builtin I2C driver"
737	depends on ARCH_UNIPHIER && DM_I2C
738	default y
739	help
740	  Support for UniPhier FIFO-builtin I2C controller driver.
741	  This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs.
742
743config SYS_I2C_VERSATILE
744	bool "Arm Ltd Versatile I2C bus driver"
745	depends on DM_I2C && TARGET_VEXPRESS64_JUNO
746	help
747	  Add support for the Arm Ltd Versatile Express I2C driver. The I2C host
748	  controller is present in the development boards manufactured by Arm Ltd.
749
750config SYS_I2C_MV
751	bool "Marvell PXA (Armada 3720) I2C driver"
752	help
753	  Support for PXA based I2C controller used on Armada 3720 SoC.
754	  In Linux, this driver is called i2c-pxa.
755
756config SYS_I2C_MVTWSI
757	bool "Marvell I2C driver"
758	depends on ARCH_KIRKWOOD || ARCH_MVEBU || ARCH_SUNXI
759	help
760	  Support for Marvell I2C controllers as used on the orion5x and
761	  kirkwood SoC families.
762
763config TEGRA186_BPMP_I2C
764	bool "Enable Tegra186 BPMP-based I2C driver"
765	depends on TEGRA186_BPMP
766	help
767	  Support for Tegra I2C controllers managed by the BPMP (Boot and
768	  Power Management Processor). On Tegra186, some I2C controllers are
769	  directly controlled by the main CPU, whereas others are controlled
770	  by the BPMP, and can only be accessed by the main CPU via IPC
771	  requests to the BPMP. This driver covers the latter case.
772
773config SYS_I2C_SLAVE
774	hex "I2C Slave address channel (all buses)"
775	depends on SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY || TPL_SYS_I2C_LEGACY
776	default 0xfe
777	help
778	  I2C Slave address channel 0 for all buses in the legacy drivers.
779	  Many boards/controllers/drivers don't support an I2C slave
780	  interface so provide a default slave address for them for use in
781	  common code.  A real value for CONFIG_SYS_I2C_SLAVE should be
782	  defined for any board which does support a slave interface and
783	  this default used otherwise.
784
785config SYS_I2C_SPEED
786	int "I2C Slave channel 0 speed (all buses)"
787	depends on SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY || TPL_SYS_I2C_LEGACY
788	default 100000
789	help
790	  I2C Slave speed channel 0 for all buses in the legacy drivers.
791
792config SYS_I2C_BUS_MAX
793	int "Max I2C busses"
794	depends on ARCH_OMAP2PLUS || ARCH_SOCFPGA
795	default 3 if OMAP34XX || AM33XX || AM43XX
796	default 4 if ARCH_SOCFPGA
797	default 5 if OMAP54XX
798	help
799	  Define the maximum number of available I2C buses.
800
801config SYS_I2C_XILINX_XIIC
802	bool "Xilinx AXI I2C driver"
803	depends on DM_I2C
804	help
805	  Support for Xilinx AXI I2C controller.
806
807config SYS_I2C_IHS
808        bool "gdsys IHS I2C driver"
809        depends on DM_I2C
810        help
811          Support for gdsys IHS I2C driver on FPGA bus.
812
813source "drivers/i2c/muxes/Kconfig"
814
815endif
816