1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * (C) Copyright 2022 - Analog Devices, Inc.
4 *
5 * Written and/or maintained by Timesys Corporation
6 *
7 * Converted to driver model by Nathan Barrett-Morrison
8 *
9 * Contact: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
10 * Contact: Greg Malysa <greg.malysa@timesys.com>
11 */
12
13 #include <clk.h>
14 #include <dm.h>
15 #include <i2c.h>
16 #include <mapmem.h>
17 #include <linux/io.h>
18
19 #define CLKLOW(x) ((x) & 0xFF) // Periods Clock Is Held Low
20 #define CLKHI(y) (((y) & 0xFF) << 0x8) // Periods Clock Is High
21
22 #define PRESCALE 0x007F // SCLKs Per Internal Time Reference (10MHz)
23 #define TWI_ENA 0x0080 // TWI Enable
24 #define SCCB 0x0200 // SCCB Compatibility Enable
25
26 #define SEN 0x0001 // Slave Enable
27 #define SADD_LEN 0x0002 // Slave Address Length
28 #define STDVAL 0x0004 // Slave Transmit Data Valid
29 #define TSC_NAK 0x0008 // NAK Generated At Conclusion Of Transfer
30 #define GEN 0x0010 // General Call Adrress Matching Enabled
31
32 #define SDIR 0x0001 // Slave Transfer Direction
33 #define GCALL 0x0002 // General Call Indicator
34
35 #define MEN 0x0001 // Master Mode Enable
36 #define MADD_LEN 0x0002 // Master Address Length
37 #define MDIR 0x0004 // Master Transmit Direction (RX/TX*)
38 #define FAST 0x0008 // Use Fast Mode Timing Specs
39 #define STOP 0x0010 // Issue Stop Condition
40 #define RSTART 0x0020 // Repeat Start or Stop* At End Of Transfer
41 #define DCNT 0x3FC0 // Data Bytes To Transfer
42 #define SDAOVR 0x4000 // Serial Data Override
43 #define SCLOVR 0x8000 // Serial Clock Override
44
45 #define MPROG 0x0001 // Master Transfer In Progress
46 #define LOSTARB 0x0002 // Lost Arbitration Indicator (Xfer Aborted)
47 #define ANAK 0x0004 // Address Not Acknowledged
48 #define DNAK 0x0008 // Data Not Acknowledged
49 #define BUFRDERR 0x0010 // Buffer Read Error
50 #define BUFWRERR 0x0020 // Buffer Write Error
51 #define SDASEN 0x0040 // Serial Data Sense
52 #define SCLSEN 0x0080 // Serial Clock Sense
53 #define BUSBUSY 0x0100 // Bus Busy Indicator
54
55 #define SINIT 0x0001 // Slave Transfer Initiated
56 #define SCOMP 0x0002 // Slave Transfer Complete
57 #define SERR 0x0004 // Slave Transfer Error
58 #define SOVF 0x0008 // Slave Overflow
59 #define MCOMP 0x0010 // Master Transfer Complete
60 #define MERR 0x0020 // Master Transfer Error
61 #define XMTSERV 0x0040 // Transmit FIFO Service
62 #define RCVSERV 0x0080 // Receive FIFO Service
63
64 #define XMTFLUSH 0x0001 // Transmit Buffer Flush
65 #define RCVFLUSH 0x0002 // Receive Buffer Flush
66 #define XMTINTLEN 0x0004 // Transmit Buffer Interrupt Length
67 #define RCVINTLEN 0x0008 // Receive Buffer Interrupt Length
68
69 #define XMTSTAT 0x0003 // Transmit FIFO Status
70 #define XMT_EMPTY 0x0000 // Transmit FIFO Empty
71 #define XMT_HALF 0x0001 // Transmit FIFO Has 1 Byte To Write
72 #define XMT_FULL 0x0003 // Transmit FIFO Full (2 Bytes To Write)
73
74 #define RCVSTAT 0x000C // Receive FIFO Status
75 #define RCV_EMPTY 0x0000 // Receive FIFO Empty
76 #define RCV_HALF 0x0004 // Receive FIFO Has 1 Byte To Read
77 #define RCV_FULL 0x000C // Receive FIFO Full (2 Bytes To Read)
78
79 /* Every register is 32bit aligned, but only 16bits in size */
80 #define ureg(name) u16 name; u16 __pad_##name
81
82 struct twi_regs {
83 ureg(clkdiv);
84 ureg(control);
85 ureg(slave_ctl);
86 ureg(slave_stat);
87 ureg(slave_addr);
88 ureg(master_ctl);
89 ureg(master_stat);
90 ureg(master_addr);
91 ureg(int_stat);
92 ureg(int_mask);
93 ureg(fifo_ctl);
94 ureg(fifo_stat);
95 u8 __pad[0x50];
96
97 ureg(xmt_data8);
98 ureg(xmt_data16);
99 ureg(rcv_data8);
100 ureg(rcv_data16);
101 };
102
103 #undef ureg
104
105 /*
106 * The way speed is changed into duty often results in integer truncation
107 * with 50% duty, so we'll force rounding up to the next duty by adding 1
108 * to the max. In practice this will get us a speed of something like
109 * 385 KHz. The other limit is easy to handle as it is only 8 bits.
110 */
111 #define I2C_SPEED_MAX 400000
112 #define I2C_SPEED_TO_DUTY(speed) (5000000 / (speed))
113 #define I2C_DUTY_MAX (I2C_SPEED_TO_DUTY(I2C_SPEED_MAX) + 1)
114 #define I2C_DUTY_MIN 0xff /* 8 bit limited */
115
116 #define I2C_M_COMBO 0x4
117 #define I2C_M_STOP 0x2
118 #define I2C_M_READ 0x1
119
120 /*
121 * All transfers are described by this data structure
122 */
123 struct adi_i2c_msg {
124 u8 flags;
125 u32 len; /* msg length */
126 u8 *buf; /* pointer to msg data */
127 u32 olen; /* addr length */
128 u8 *obuf; /* addr buffer */
129 };
130
131 struct adi_i2c_dev {
132 struct twi_regs __iomem *base;
133 u32 i2c_clk;
134 uint speed;
135 };
136
137 /* Allow msec timeout per ~byte transfer */
138 #define I2C_TIMEOUT 10
139
140 /**
141 * wait_for_completion - manage the actual i2c transfer
142 * @msg: the i2c msg
143 */
wait_for_completion(struct twi_regs * twi,struct adi_i2c_msg * msg)144 static int wait_for_completion(struct twi_regs *twi, struct adi_i2c_msg *msg)
145 {
146 u16 int_stat;
147 ulong timebase = get_timer(0);
148
149 do {
150 int_stat = ioread16(&twi->int_stat);
151
152 if (int_stat & XMTSERV) {
153 iowrite16(XMTSERV, &twi->int_stat);
154 if (msg->olen) {
155 iowrite16(*(msg->obuf++), &twi->xmt_data8);
156 --msg->olen;
157 } else if (!(msg->flags & I2C_M_COMBO) && msg->len) {
158 iowrite16(*(msg->buf++), &twi->xmt_data8);
159 --msg->len;
160 } else {
161 if (msg->flags & I2C_M_COMBO)
162 setbits_16(&twi->master_ctl, RSTART | MDIR);
163 else
164 setbits_16(&twi->master_ctl, STOP);
165 }
166 }
167 if (int_stat & RCVSERV) {
168 iowrite16(RCVSERV, &twi->int_stat);
169 if (msg->len) {
170 *(msg->buf++) = ioread16(&twi->rcv_data8);
171 --msg->len;
172 } else if (msg->flags & I2C_M_STOP) {
173 setbits_16(&twi->master_ctl, STOP);
174 }
175 }
176 if (int_stat & MERR) {
177 pr_err("%s: master transmit terror: %d\n", __func__,
178 ioread16(&twi->master_stat));
179 iowrite16(MERR, &twi->int_stat);
180 return -EIO;
181 }
182 if (int_stat & MCOMP) {
183 iowrite16(MCOMP, &twi->int_stat);
184 if (msg->flags & I2C_M_COMBO && msg->len) {
185 u16 mlen = min(msg->len, 0xffu) << 6;
186 clrsetbits_16(&twi->master_ctl, RSTART, mlen | MEN | MDIR);
187 } else {
188 break;
189 }
190 }
191
192 /* If we were able to do something, reset timeout */
193 if (int_stat)
194 timebase = get_timer(0);
195
196 } while (get_timer(timebase) < I2C_TIMEOUT);
197
198 return 0;
199 }
200
i2c_transfer(struct twi_regs * twi,u8 chip,u8 * offset,int olen,u8 * buffer,int len,u8 flags)201 static int i2c_transfer(struct twi_regs *twi, u8 chip, u8 *offset,
202 int olen, u8 *buffer, int len, u8 flags)
203 {
204 int ret;
205 u16 ctl;
206
207 struct adi_i2c_msg msg = {
208 .flags = flags | (len >= 0xff ? I2C_M_STOP : 0),
209 .buf = buffer,
210 .len = len,
211 .obuf = offset,
212 .olen = olen,
213 };
214
215 /* wait for things to settle */
216 while (ioread16(&twi->master_stat) & BUSBUSY)
217 if (!IS_ENABLED(CONFIG_SPL_BUILD) && ctrlc())
218 return -EINTR;
219
220 /* Set Transmit device address */
221 iowrite16(chip, &twi->master_addr);
222
223 /* Clear the FIFO before starting things */
224 iowrite16(XMTFLUSH | RCVFLUSH, &twi->fifo_ctl);
225 iowrite16(0, &twi->fifo_ctl);
226
227 /* Prime the pump */
228 if (msg.olen) {
229 len = (msg.flags & I2C_M_COMBO) ? msg.olen : msg.olen + len;
230 iowrite16(*(msg.obuf++), &twi->xmt_data8);
231 --msg.olen;
232 } else if (!(msg.flags & I2C_M_READ) && msg.len) {
233 iowrite16(*(msg.buf++), &twi->xmt_data8);
234 --msg.len;
235 }
236
237 /* clear int stat */
238 iowrite16(-1, &twi->master_stat);
239 iowrite16(-1, &twi->int_stat);
240 iowrite16(0, &twi->int_mask);
241
242 /* Master enable */
243 ctl = ioread16(&twi->master_ctl);
244 ctl = (ctl & FAST) | (min(len, 0xff) << 6) | MEN |
245 ((msg.flags & I2C_M_READ) ? MDIR : 0);
246 iowrite16(ctl, &twi->master_ctl);
247
248 /* Process the rest */
249 ret = wait_for_completion(twi, &msg);
250
251 clrbits_16(&twi->master_ctl, MEN);
252 clrbits_16(&twi->control, TWI_ENA);
253 setbits_16(&twi->control, TWI_ENA);
254 return ret;
255 }
256
adi_i2c_read(struct twi_regs * twi,u8 chip,u8 * offset,int olen,u8 * buffer,int len)257 static int adi_i2c_read(struct twi_regs *twi, u8 chip,
258 u8 *offset, int olen, u8 *buffer, int len)
259 {
260 return i2c_transfer(twi, chip, offset, olen, buffer,
261 len, olen ? I2C_M_COMBO : I2C_M_READ);
262 }
263
adi_i2c_write(struct twi_regs * twi,u8 chip,u8 * offset,int olen,u8 * buffer,int len)264 static int adi_i2c_write(struct twi_regs *twi, u8 chip,
265 u8 *offset, int olen, u8 *buffer, int len)
266 {
267 return i2c_transfer(twi, chip, offset, olen, buffer, len, 0);
268 }
269
adi_i2c_set_bus_speed(struct udevice * bus,uint speed)270 static int adi_i2c_set_bus_speed(struct udevice *bus, uint speed)
271 {
272 struct adi_i2c_dev *dev = dev_get_priv(bus);
273 struct twi_regs *twi = dev->base;
274 u16 clkdiv = I2C_SPEED_TO_DUTY(speed);
275
276 /* Set TWI interface clock */
277 if (clkdiv < I2C_DUTY_MAX || clkdiv > I2C_DUTY_MIN)
278 return -1;
279 clkdiv = (clkdiv << 8) | (clkdiv & 0xff);
280 iowrite16(clkdiv, &twi->clkdiv);
281
282 /* Don't turn it on */
283 iowrite16(speed > 100000 ? FAST : 0, &twi->master_ctl);
284
285 return 0;
286 }
287
adi_i2c_of_to_plat(struct udevice * bus)288 static int adi_i2c_of_to_plat(struct udevice *bus)
289 {
290 struct adi_i2c_dev *dev = dev_get_priv(bus);
291 struct clk clock;
292 u32 ret;
293
294 dev->base = map_sysmem(dev_read_addr(bus), sizeof(struct twi_regs));
295
296 if (!dev->base)
297 return -ENOMEM;
298
299 dev->speed = dev_read_u32_default(bus, "clock-frequency",
300 I2C_SPEED_FAST_RATE);
301
302 ret = clk_get_by_name(bus, "i2c", &clock);
303 if (ret < 0)
304 printf("%s: Can't get I2C clk: %d\n", __func__, ret);
305 else
306 dev->i2c_clk = clk_get_rate(&clock);
307
308 return 0;
309 }
310
adi_i2c_probe_chip(struct udevice * bus,u32 chip_addr,u32 chip_flags)311 static int adi_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
312 u32 chip_flags)
313 {
314 struct adi_i2c_dev *dev = dev_get_priv(bus);
315 u8 byte;
316
317 return adi_i2c_read(dev->base, chip_addr, NULL, 0, &byte, 1);
318 }
319
adi_i2c_xfer(struct udevice * bus,struct i2c_msg * msg,int nmsgs)320 static int adi_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
321 {
322 struct adi_i2c_dev *dev = dev_get_priv(bus);
323 struct i2c_msg *dmsg, *omsg, dummy;
324
325 memset(&dummy, 0, sizeof(struct i2c_msg));
326
327 /*
328 * We expect either two messages (one with an offset and one with the
329 * actual data) or one message (just data)
330 */
331 if (nmsgs > 2 || nmsgs == 0) {
332 debug("%s: Only one or two messages are supported.", __func__);
333 return -EINVAL;
334 }
335
336 omsg = nmsgs == 1 ? &dummy : msg;
337 dmsg = nmsgs == 1 ? msg : msg + 1;
338
339 if (dmsg->flags & I2C_M_RD)
340 return adi_i2c_read(dev->base, dmsg->addr, omsg->buf, omsg->len,
341 dmsg->buf, dmsg->len);
342 else
343 return adi_i2c_write(dev->base, dmsg->addr, omsg->buf, omsg->len,
344 dmsg->buf, dmsg->len);
345 }
346
adi_i2c_probe(struct udevice * bus)347 int adi_i2c_probe(struct udevice *bus)
348 {
349 struct adi_i2c_dev *dev = dev_get_priv(bus);
350 struct twi_regs *twi = dev->base;
351
352 u16 prescale = ((dev->i2c_clk / 1000 / 1000 + 5) / 10) & 0x7F;
353
354 /* Set TWI internal clock as 10MHz */
355 iowrite16(prescale, &twi->control);
356
357 /* Set TWI interface clock as specified */
358 adi_i2c_set_bus_speed(bus, dev->speed);
359
360 /* Enable it */
361 iowrite16(TWI_ENA | prescale, &twi->control);
362
363 return 0;
364 }
365
366 static const struct dm_i2c_ops adi_i2c_ops = {
367 .xfer = adi_i2c_xfer,
368 .probe_chip = adi_i2c_probe_chip,
369 .set_bus_speed = adi_i2c_set_bus_speed,
370 };
371
372 static const struct udevice_id adi_i2c_ids[] = {
373 { .compatible = "adi-i2c", },
374 { /* sentinel */ }
375 };
376
377 U_BOOT_DRIVER(i2c_adi) = {
378 .name = "i2c_adi",
379 .id = UCLASS_I2C,
380 .of_match = adi_i2c_ids,
381 .probe = adi_i2c_probe,
382 .of_to_plat = adi_i2c_of_to_plat,
383 .priv_auto = sizeof(struct adi_i2c_dev),
384 .ops = &adi_i2c_ops,
385 .flags = DM_FLAG_PRE_RELOC,
386 };
387