1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2012-2020 ASPEED Technology Inc.
4 * Copyright 2016 IBM Corporation
5 * Copyright 2017 Google, Inc.
6 */
7
8 #include <clk.h>
9 #include <dm.h>
10 #include <errno.h>
11 #include <fdtdec.h>
12 #include <i2c.h>
13 #include <log.h>
14 #include <asm/io.h>
15 #include <asm/arch/scu_ast2500.h>
16 #include <linux/delay.h>
17 #include <linux/err.h>
18 #include <reset.h>
19
20 #include "ast_i2c.h"
21
22 #define I2C_TIMEOUT_US 100000
23 #define I2C_SLEEP_STEP_US 20
24
25 #define HIGHSPEED_TTIMEOUT 3
26
27 /*
28 * Device private data
29 */
30 struct ast_i2c_priv {
31 /* This device's clock */
32 struct clk clk;
33 /* Device registers */
34 struct ast_i2c_regs *regs;
35 /* I2C speed in Hz */
36 int speed;
37 };
38
39 /*
40 * Given desired divider ratio, return the value that needs to be set
41 * in Clock and AC Timing Control register
42 */
get_clk_reg_val(ulong divider_ratio)43 static u32 get_clk_reg_val(ulong divider_ratio)
44 {
45 ulong inc = 0, div;
46 ulong scl_low, scl_high, data;
47
48 for (div = 0; divider_ratio >= 16; div++) {
49 inc |= (divider_ratio & 1);
50 divider_ratio >>= 1;
51 }
52 divider_ratio += inc;
53 scl_low = (divider_ratio >> 1) - 1;
54 scl_high = divider_ratio - scl_low - 2;
55 data = I2CD_CACTC_BASE
56 | (scl_high << I2CD_TCKHIGH_SHIFT)
57 | (scl_low << I2CD_TCKLOW_SHIFT)
58 | (div << I2CD_BASE_DIV_SHIFT);
59
60 return data;
61 }
62
ast_i2c_clear_interrupts(struct udevice * dev)63 static void ast_i2c_clear_interrupts(struct udevice *dev)
64 {
65 struct ast_i2c_priv *priv = dev_get_priv(dev);
66
67 writel(~0, &priv->regs->isr);
68 }
69
ast_i2c_init_bus(struct udevice * dev)70 static void ast_i2c_init_bus(struct udevice *dev)
71 {
72 struct ast_i2c_priv *priv = dev_get_priv(dev);
73
74 /* Reset device */
75 writel(0, &priv->regs->fcr);
76 /* Enable Master Mode. Assuming single-master */
77 writel(I2CD_MASTER_EN
78 | I2CD_M_SDA_LOCK_EN
79 | I2CD_MULTI_MASTER_DIS,
80 &priv->regs->fcr);
81 /* Enable Interrupts */
82 writel(I2CD_INTR_TX_ACK
83 | I2CD_INTR_TX_NAK
84 | I2CD_INTR_RX_DONE
85 | I2CD_INTR_BUS_RECOVER_DONE
86 | I2CD_INTR_NORMAL_STOP
87 | I2CD_INTR_ABNORMAL, &priv->regs->icr);
88 }
89
ast_i2c_of_to_plat(struct udevice * dev)90 static int ast_i2c_of_to_plat(struct udevice *dev)
91 {
92 struct ast_i2c_priv *priv = dev_get_priv(dev);
93 int ret;
94
95 priv->regs = dev_read_addr_ptr(dev);
96 if (!priv->regs)
97 return -EINVAL;
98
99 ret = clk_get_by_index(dev, 0, &priv->clk);
100 if (ret < 0) {
101 debug("%s: Can't get clock for %s: %d\n", __func__, dev->name,
102 ret);
103 return ret;
104 }
105
106 return 0;
107 }
108
ast_i2c_probe(struct udevice * dev)109 static int ast_i2c_probe(struct udevice *dev)
110 {
111 struct reset_ctl reset_ctl;
112 int rc;
113
114 debug("Enabling I2C%u\n", dev_seq(dev));
115
116 /*
117 * Get all I2C devices out of Reset.
118 *
119 * Only needs to be done once so test before performing reset.
120 */
121 rc = reset_get_by_index(dev, 0, &reset_ctl);
122 if (rc) {
123 printf("%s: Failed to get reset signal\n", __func__);
124 return rc;
125 }
126
127 if (reset_status(&reset_ctl) > 0) {
128 reset_assert(&reset_ctl);
129 reset_deassert(&reset_ctl);
130 }
131
132 ast_i2c_init_bus(dev);
133
134 return 0;
135 }
136
ast_i2c_wait_isr(struct udevice * dev,u32 flag)137 static int ast_i2c_wait_isr(struct udevice *dev, u32 flag)
138 {
139 struct ast_i2c_priv *priv = dev_get_priv(dev);
140 int timeout = I2C_TIMEOUT_US;
141
142 while (!(readl(&priv->regs->isr) & flag) && timeout > 0) {
143 udelay(I2C_SLEEP_STEP_US);
144 timeout -= I2C_SLEEP_STEP_US;
145 }
146
147 ast_i2c_clear_interrupts(dev);
148 if (timeout <= 0)
149 return -ETIMEDOUT;
150
151 return 0;
152 }
153
ast_i2c_send_stop(struct udevice * dev)154 static int ast_i2c_send_stop(struct udevice *dev)
155 {
156 struct ast_i2c_priv *priv = dev_get_priv(dev);
157
158 writel(I2CD_M_STOP_CMD, &priv->regs->csr);
159
160 return ast_i2c_wait_isr(dev, I2CD_INTR_NORMAL_STOP);
161 }
162
ast_i2c_wait_tx(struct udevice * dev)163 static int ast_i2c_wait_tx(struct udevice *dev)
164 {
165 struct ast_i2c_priv *priv = dev_get_priv(dev);
166 int timeout = I2C_TIMEOUT_US;
167 u32 flag = I2CD_INTR_TX_ACK | I2CD_INTR_TX_NAK;
168 u32 status = readl(&priv->regs->isr) & flag;
169 int ret = 0;
170
171 while (!status && timeout > 0) {
172 status = readl(&priv->regs->isr) & flag;
173 udelay(I2C_SLEEP_STEP_US);
174 timeout -= I2C_SLEEP_STEP_US;
175 }
176
177 if (status == I2CD_INTR_TX_NAK)
178 ret = -EREMOTEIO;
179
180 if (timeout <= 0)
181 ret = -ETIMEDOUT;
182
183 ast_i2c_clear_interrupts(dev);
184
185 return ret;
186 }
187
ast_i2c_start_txn(struct udevice * dev,uint devaddr)188 static int ast_i2c_start_txn(struct udevice *dev, uint devaddr)
189 {
190 struct ast_i2c_priv *priv = dev_get_priv(dev);
191
192 /* Start and Send Device Address */
193 writel(devaddr, &priv->regs->trbbr);
194 writel(I2CD_M_START_CMD | I2CD_M_TX_CMD, &priv->regs->csr);
195
196 return ast_i2c_wait_tx(dev);
197 }
198
ast_i2c_read_data(struct udevice * dev,u8 chip_addr,u8 * buffer,size_t len,bool send_stop)199 static int ast_i2c_read_data(struct udevice *dev, u8 chip_addr, u8 *buffer,
200 size_t len, bool send_stop)
201 {
202 struct ast_i2c_priv *priv = dev_get_priv(dev);
203 u32 i2c_cmd = I2CD_M_RX_CMD;
204 int ret;
205
206 ret = ast_i2c_start_txn(dev, (chip_addr << 1) | I2C_M_RD);
207 if (ret < 0)
208 return ret;
209
210 for (; len > 0; len--, buffer++) {
211 if (len == 1)
212 i2c_cmd |= I2CD_M_S_RX_CMD_LAST;
213 writel(i2c_cmd, &priv->regs->csr);
214 ret = ast_i2c_wait_isr(dev, I2CD_INTR_RX_DONE);
215 if (ret < 0)
216 return ret;
217 *buffer = (readl(&priv->regs->trbbr) & I2CD_RX_DATA_MASK)
218 >> I2CD_RX_DATA_SHIFT;
219 }
220 ast_i2c_clear_interrupts(dev);
221
222 if (send_stop)
223 return ast_i2c_send_stop(dev);
224
225 return 0;
226 }
227
ast_i2c_write_data(struct udevice * dev,u8 chip_addr,u8 * buffer,size_t len,bool send_stop)228 static int ast_i2c_write_data(struct udevice *dev, u8 chip_addr, u8
229 *buffer, size_t len, bool send_stop)
230 {
231 struct ast_i2c_priv *priv = dev_get_priv(dev);
232 int ret;
233
234 ret = ast_i2c_start_txn(dev, (chip_addr << 1));
235 if (ret < 0)
236 return ret;
237
238 for (; len > 0; len--, buffer++) {
239 writel(*buffer, &priv->regs->trbbr);
240 writel(I2CD_M_TX_CMD, &priv->regs->csr);
241 ret = ast_i2c_wait_tx(dev);
242 if (ret < 0)
243 return ret;
244 }
245
246 if (send_stop)
247 return ast_i2c_send_stop(dev);
248
249 return 0;
250 }
251
ast_i2c_deblock(struct udevice * dev)252 static int ast_i2c_deblock(struct udevice *dev)
253 {
254 struct ast_i2c_priv *priv = dev_get_priv(dev);
255 struct ast_i2c_regs *regs = priv->regs;
256 u32 csr = readl(®s->csr);
257 bool sda_high = csr & I2CD_SDA_LINE_STS;
258 bool scl_high = csr & I2CD_SCL_LINE_STS;
259 int ret = 0;
260
261 if (sda_high && scl_high) {
262 /* Bus is idle, no deblocking needed. */
263 return 0;
264 } else if (sda_high) {
265 /* Send stop command */
266 debug("Unterminated TXN in (%x), sending stop\n", csr);
267 ret = ast_i2c_send_stop(dev);
268 } else if (scl_high) {
269 /* Possibly stuck slave */
270 debug("Bus stuck (%x), attempting recovery\n", csr);
271 writel(I2CD_BUS_RECOVER_CMD, ®s->csr);
272 ret = ast_i2c_wait_isr(dev, I2CD_INTR_BUS_RECOVER_DONE);
273 } else {
274 /* Just try to reinit the device. */
275 ast_i2c_init_bus(dev);
276 }
277
278 return ret;
279 }
280
ast_i2c_xfer(struct udevice * dev,struct i2c_msg * msg,int nmsgs)281 static int ast_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs)
282 {
283 int ret;
284
285 ret = ast_i2c_deblock(dev);
286 if (ret < 0)
287 return ret;
288
289 debug("i2c_xfer: %d messages\n", nmsgs);
290 for (; nmsgs > 0; nmsgs--, msg++) {
291 if (msg->flags & I2C_M_RD) {
292 debug("i2c_read: chip=0x%x, len=0x%x, flags=0x%x\n",
293 msg->addr, msg->len, msg->flags);
294 ret = ast_i2c_read_data(dev, msg->addr, msg->buf,
295 msg->len, (nmsgs == 1));
296 } else {
297 debug("i2c_write: chip=0x%x, len=0x%x, flags=0x%x\n",
298 msg->addr, msg->len, msg->flags);
299 ret = ast_i2c_write_data(dev, msg->addr, msg->buf,
300 msg->len, (nmsgs == 1));
301 }
302 if (ret) {
303 debug("%s: error (%d)\n", __func__, ret);
304 return -EREMOTEIO;
305 }
306 }
307
308 return 0;
309 }
310
ast_i2c_set_speed(struct udevice * dev,unsigned int speed)311 static int ast_i2c_set_speed(struct udevice *dev, unsigned int speed)
312 {
313 struct ast_i2c_priv *priv = dev_get_priv(dev);
314 struct ast_i2c_regs *regs = priv->regs;
315 ulong i2c_rate, divider;
316
317 debug("Setting speed for I2C%d to <%u>\n", dev_seq(dev), speed);
318 if (!speed) {
319 debug("No valid speed specified\n");
320 return -EINVAL;
321 }
322
323 i2c_rate = clk_get_rate(&priv->clk);
324 divider = i2c_rate / speed;
325
326 priv->speed = speed;
327 if (speed > I2C_SPEED_FAST_RATE) {
328 debug("Enable High Speed\n");
329 setbits_le32(®s->fcr, I2CD_M_HIGH_SPEED_EN
330 | I2CD_M_SDA_DRIVE_1T_EN
331 | I2CD_SDA_DRIVE_1T_EN);
332 writel(HIGHSPEED_TTIMEOUT, ®s->cactcr2);
333 } else {
334 debug("Enabling Normal Speed\n");
335 writel(I2CD_NO_TIMEOUT_CTRL, ®s->cactcr2);
336 }
337
338 writel(get_clk_reg_val(divider), ®s->cactcr1);
339 ast_i2c_clear_interrupts(dev);
340
341 return 0;
342 }
343
344 static const struct dm_i2c_ops ast_i2c_ops = {
345 .xfer = ast_i2c_xfer,
346 .set_bus_speed = ast_i2c_set_speed,
347 .deblock = ast_i2c_deblock,
348 };
349
350 static const struct udevice_id ast_i2c_ids[] = {
351 { .compatible = "aspeed,ast2400-i2c-bus" },
352 { .compatible = "aspeed,ast2500-i2c-bus" },
353 { .compatible = "aspeed,ast2600-i2c-bus" },
354 { },
355 };
356
357 U_BOOT_DRIVER(ast_i2c) = {
358 .name = "ast_i2c",
359 .id = UCLASS_I2C,
360 .of_match = ast_i2c_ids,
361 .probe = ast_i2c_probe,
362 .of_to_plat = ast_i2c_of_to_plat,
363 .priv_auto = sizeof(struct ast_i2c_priv),
364 .ops = &ast_i2c_ops,
365 };
366