1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2015 Moritz Fischer <moritz.fischer@ettus.com>
4 * IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2)
5 *
6 * This file is based on: drivers/i2c/zynq_i2c.c,
7 * with added driver-model support and code cleanup.
8 */
9
10 #include <dm.h>
11 #include <log.h>
12 #include <linux/bitops.h>
13 #include <linux/delay.h>
14 #include <linux/types.h>
15 #include <linux/io.h>
16 #include <linux/errno.h>
17 #include <dm/device_compat.h>
18 #include <dm/root.h>
19 #include <i2c.h>
20 #include <fdtdec.h>
21 #include <mapmem.h>
22 #include <wait_bit.h>
23 #include <clk.h>
24
25 /* i2c register set */
26 struct cdns_i2c_regs {
27 u32 control;
28 u32 status;
29 u32 address;
30 u32 data;
31 u32 interrupt_status;
32 u32 transfer_size;
33 u32 slave_mon_pause;
34 u32 time_out;
35 u32 interrupt_mask;
36 u32 interrupt_enable;
37 u32 interrupt_disable;
38 };
39
40 /* Control register fields */
41 #define CDNS_I2C_CONTROL_RW 0x00000001
42 #define CDNS_I2C_CONTROL_MS 0x00000002
43 #define CDNS_I2C_CONTROL_NEA 0x00000004
44 #define CDNS_I2C_CONTROL_ACKEN 0x00000008
45 #define CDNS_I2C_CONTROL_HOLD 0x00000010
46 #define CDNS_I2C_CONTROL_SLVMON 0x00000020
47 #define CDNS_I2C_CONTROL_CLR_FIFO 0x00000040
48 #define CDNS_I2C_CONTROL_DIV_B_SHIFT 8
49 #define CDNS_I2C_CONTROL_DIV_B_MASK 0x00003F00
50 #define CDNS_I2C_CONTROL_DIV_A_SHIFT 14
51 #define CDNS_I2C_CONTROL_DIV_A_MASK 0x0000C000
52
53 /* Status register values */
54 #define CDNS_I2C_STATUS_RXDV 0x00000020
55 #define CDNS_I2C_STATUS_TXDV 0x00000040
56 #define CDNS_I2C_STATUS_RXOVF 0x00000080
57 #define CDNS_I2C_STATUS_BA 0x00000100
58
59 /* Interrupt register fields */
60 #define CDNS_I2C_INTERRUPT_COMP 0x00000001
61 #define CDNS_I2C_INTERRUPT_DATA 0x00000002
62 #define CDNS_I2C_INTERRUPT_NACK 0x00000004
63 #define CDNS_I2C_INTERRUPT_TO 0x00000008
64 #define CDNS_I2C_INTERRUPT_SLVRDY 0x00000010
65 #define CDNS_I2C_INTERRUPT_RXOVF 0x00000020
66 #define CDNS_I2C_INTERRUPT_TXOVF 0x00000040
67 #define CDNS_I2C_INTERRUPT_RXUNF 0x00000080
68 #define CDNS_I2C_INTERRUPT_ARBLOST 0x00000200
69
70 #define CDNS_I2C_INTERRUPTS_MASK (CDNS_I2C_INTERRUPT_COMP | \
71 CDNS_I2C_INTERRUPT_DATA | \
72 CDNS_I2C_INTERRUPT_NACK | \
73 CDNS_I2C_INTERRUPT_TO | \
74 CDNS_I2C_INTERRUPT_SLVRDY | \
75 CDNS_I2C_INTERRUPT_RXOVF | \
76 CDNS_I2C_INTERRUPT_TXOVF | \
77 CDNS_I2C_INTERRUPT_RXUNF | \
78 CDNS_I2C_INTERRUPT_ARBLOST)
79
80 #define CDNS_I2C_FIFO_DEPTH_DEFAULT 16
81 #define CDNS_I2C_TRANSFER_SIZE_MAX 255 /* Controller transfer limit */
82 #define CDNS_I2C_TRANSFER_SIZE (CDNS_I2C_TRANSFER_SIZE_MAX - 3)
83
84 #define CDNS_I2C_BROKEN_HOLD_BIT BIT(0)
85
86 #define CDNS_I2C_ARB_LOST_MAX_RETRIES 10
87
88 #ifdef DEBUG
cdns_i2c_debug_status(struct cdns_i2c_regs * cdns_i2c)89 static void cdns_i2c_debug_status(struct cdns_i2c_regs *cdns_i2c)
90 {
91 int int_status;
92 int status;
93 int_status = readl(&cdns_i2c->interrupt_status);
94
95 status = readl(&cdns_i2c->status);
96 if (int_status || status) {
97 debug("Status: ");
98 if (int_status & CDNS_I2C_INTERRUPT_COMP)
99 debug("COMP ");
100 if (int_status & CDNS_I2C_INTERRUPT_DATA)
101 debug("DATA ");
102 if (int_status & CDNS_I2C_INTERRUPT_NACK)
103 debug("NACK ");
104 if (int_status & CDNS_I2C_INTERRUPT_TO)
105 debug("TO ");
106 if (int_status & CDNS_I2C_INTERRUPT_SLVRDY)
107 debug("SLVRDY ");
108 if (int_status & CDNS_I2C_INTERRUPT_RXOVF)
109 debug("RXOVF ");
110 if (int_status & CDNS_I2C_INTERRUPT_TXOVF)
111 debug("TXOVF ");
112 if (int_status & CDNS_I2C_INTERRUPT_RXUNF)
113 debug("RXUNF ");
114 if (int_status & CDNS_I2C_INTERRUPT_ARBLOST)
115 debug("ARBLOST ");
116 if (status & CDNS_I2C_STATUS_RXDV)
117 debug("RXDV ");
118 if (status & CDNS_I2C_STATUS_TXDV)
119 debug("TXDV ");
120 if (status & CDNS_I2C_STATUS_RXOVF)
121 debug("RXOVF ");
122 if (status & CDNS_I2C_STATUS_BA)
123 debug("BA ");
124 debug("TS%d ", readl(&cdns_i2c->transfer_size));
125 debug("\n");
126 }
127 }
128 #endif
129
130 struct i2c_cdns_bus {
131 int id;
132 unsigned int input_freq;
133 struct cdns_i2c_regs __iomem *regs; /* register base */
134
135 int hold_flag;
136 u32 quirks;
137 u32 fifo_depth;
138 };
139
140 struct cdns_i2c_platform_data {
141 u32 quirks;
142 };
143
144 /* Wait for an interrupt */
cdns_i2c_wait(struct cdns_i2c_regs * cdns_i2c,u32 mask)145 static u32 cdns_i2c_wait(struct cdns_i2c_regs *cdns_i2c, u32 mask)
146 {
147 int timeout, int_status;
148
149 for (timeout = 0; timeout < 100; timeout++) {
150 int_status = readl(&cdns_i2c->interrupt_status);
151 if (int_status & mask)
152 break;
153 udelay(100);
154 }
155
156 /* Clear interrupt status flags */
157 writel(int_status & mask, &cdns_i2c->interrupt_status);
158
159 return int_status & mask;
160 }
161
162 #define CDNS_I2C_DIVA_MAX 4
163 #define CDNS_I2C_DIVB_MAX 64
164
cdns_i2c_calc_divs(unsigned long * f,unsigned long input_clk,unsigned int * a,unsigned int * b)165 static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk,
166 unsigned int *a, unsigned int *b)
167 {
168 unsigned long fscl = *f, best_fscl = *f, actual_fscl, temp;
169 unsigned int div_a, div_b, calc_div_a = 0, calc_div_b = 0;
170 unsigned int last_error, current_error;
171
172 /* calculate (divisor_a+1) x (divisor_b+1) */
173 temp = input_clk / (22 * fscl);
174
175 /*
176 * If the calculated value is negative or 0CDNS_I2C_DIVA_MAX,
177 * the fscl input is out of range. Return error.
178 */
179 if (!temp || (temp > (CDNS_I2C_DIVA_MAX * CDNS_I2C_DIVB_MAX)))
180 return -EINVAL;
181
182 last_error = -1;
183 for (div_a = 0; div_a < CDNS_I2C_DIVA_MAX; div_a++) {
184 div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1));
185
186 if ((div_b < 1) || (div_b > CDNS_I2C_DIVB_MAX))
187 continue;
188 div_b--;
189
190 actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1));
191
192 if (actual_fscl > fscl)
193 continue;
194
195 current_error = ((actual_fscl > fscl) ? (actual_fscl - fscl) :
196 (fscl - actual_fscl));
197
198 if (last_error > current_error) {
199 calc_div_a = div_a;
200 calc_div_b = div_b;
201 best_fscl = actual_fscl;
202 last_error = current_error;
203 }
204 }
205
206 *a = calc_div_a;
207 *b = calc_div_b;
208 *f = best_fscl;
209
210 return 0;
211 }
212
cdns_i2c_set_bus_speed(struct udevice * dev,unsigned int speed)213 static int cdns_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
214 {
215 struct i2c_cdns_bus *bus = dev_get_priv(dev);
216 u32 div_a = 0, div_b = 0;
217 unsigned long speed_p = speed;
218 int ret = 0;
219
220 if (speed > I2C_SPEED_FAST_RATE) {
221 debug("%s, failed to set clock speed to %u\n", __func__,
222 speed);
223 return -EINVAL;
224 }
225
226 ret = cdns_i2c_calc_divs(&speed_p, bus->input_freq, &div_a, &div_b);
227 if (ret)
228 return ret;
229
230 debug("%s: div_a: %d, div_b: %d, input freq: %d, speed: %d/%ld\n",
231 __func__, div_a, div_b, bus->input_freq, speed, speed_p);
232
233 writel((div_b << CDNS_I2C_CONTROL_DIV_B_SHIFT) |
234 (div_a << CDNS_I2C_CONTROL_DIV_A_SHIFT), &bus->regs->control);
235
236 /* Enable master mode, ack, and 7-bit addressing */
237 setbits_le32(&bus->regs->control, CDNS_I2C_CONTROL_MS |
238 CDNS_I2C_CONTROL_ACKEN | CDNS_I2C_CONTROL_NEA);
239
240 return 0;
241 }
242
is_arbitration_lost(struct cdns_i2c_regs * regs)243 static inline u32 is_arbitration_lost(struct cdns_i2c_regs *regs)
244 {
245 return (readl(®s->interrupt_status) & CDNS_I2C_INTERRUPT_ARBLOST);
246 }
247
cdns_i2c_write_data(struct i2c_cdns_bus * i2c_bus,u32 addr,u8 * data,u32 len)248 static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
249 u32 len)
250 {
251 u8 *cur_data = data;
252 struct cdns_i2c_regs *regs = i2c_bus->regs;
253 u32 ret;
254 bool start = 1;
255
256 /* Set the controller in Master transmit mode and clear FIFO */
257 setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO);
258 clrbits_le32(®s->control, CDNS_I2C_CONTROL_RW);
259
260 /*
261 * For sequential data load hold the bus.
262 */
263 if (len > 1)
264 setbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
265
266 /* Clear the interrupts in status register */
267 writel(CDNS_I2C_INTERRUPTS_MASK, ®s->interrupt_status);
268
269 /* In case of Probe (i.e no data), start the transfer */
270 if (!len)
271 writel(addr, ®s->address);
272
273 while (len-- && !is_arbitration_lost(regs)) {
274 writel(*(cur_data++), ®s->data);
275 /* Trigger write only after loading data */
276 if (start) {
277 writel(addr, ®s->address);
278 start = 0;
279 }
280 if (len && readl(®s->transfer_size) == i2c_bus->fifo_depth) {
281 ret = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
282 CDNS_I2C_INTERRUPT_ARBLOST);
283 if (ret & CDNS_I2C_INTERRUPT_ARBLOST)
284 return -EAGAIN;
285 if (ret & CDNS_I2C_INTERRUPT_COMP)
286 continue;
287 /* Release the bus */
288 clrbits_le32(®s->control,
289 CDNS_I2C_CONTROL_HOLD);
290 return -ETIMEDOUT;
291 }
292 }
293
294 if (len && is_arbitration_lost(regs))
295 return -EAGAIN;
296
297 /* All done... release the bus */
298 if (!i2c_bus->hold_flag)
299 clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
300
301 /* Wait for the address and data to be sent */
302 ret = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
303 CDNS_I2C_INTERRUPT_ARBLOST);
304 if (!(ret & (CDNS_I2C_INTERRUPT_ARBLOST |
305 CDNS_I2C_INTERRUPT_COMP)))
306 return -ETIMEDOUT;
307 if (ret & CDNS_I2C_INTERRUPT_ARBLOST)
308 return -EAGAIN;
309
310 return 0;
311 }
312
cdns_is_hold_quirk(struct i2c_cdns_bus * i2c_bus,int hold_quirk,int curr_recv_count)313 static inline bool cdns_is_hold_quirk(struct i2c_cdns_bus *i2c_bus, int hold_quirk,
314 int curr_recv_count)
315 {
316 return hold_quirk && (curr_recv_count == i2c_bus->fifo_depth + 1);
317 }
318
cdns_i2c_read_data(struct i2c_cdns_bus * i2c_bus,u32 addr,u8 * data,u32 recv_count)319 static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
320 u32 recv_count)
321 {
322 u8 *cur_data = data;
323 struct cdns_i2c_regs *regs = i2c_bus->regs;
324 u32 curr_recv_count;
325 int updatetx, hold_quirk;
326 u32 ret;
327
328 curr_recv_count = recv_count;
329
330 /* Check for the message size against the FIFO depth */
331 if (recv_count > i2c_bus->fifo_depth)
332 setbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD);
333
334 setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO |
335 CDNS_I2C_CONTROL_RW);
336
337 if (recv_count > CDNS_I2C_TRANSFER_SIZE) {
338 curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
339 writel(curr_recv_count, ®s->transfer_size);
340 } else {
341 writel(recv_count, ®s->transfer_size);
342 }
343
344 /* Start reading data */
345 writel(addr, ®s->address);
346
347 updatetx = recv_count > curr_recv_count;
348
349 hold_quirk = (i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT) && updatetx;
350
351 while (recv_count && !is_arbitration_lost(regs)) {
352 while (readl(®s->status) & CDNS_I2C_STATUS_RXDV) {
353 if (recv_count < i2c_bus->fifo_depth &&
354 !i2c_bus->hold_flag) {
355 clrbits_le32(®s->control,
356 CDNS_I2C_CONTROL_HOLD);
357 }
358 *(cur_data)++ = readl(®s->data);
359 recv_count--;
360 curr_recv_count--;
361
362 if (cdns_is_hold_quirk(i2c_bus, hold_quirk, curr_recv_count))
363 break;
364 }
365
366 if (cdns_is_hold_quirk(i2c_bus, hold_quirk, curr_recv_count)) {
367 /* wait while fifo is full */
368 while (readl(®s->transfer_size) !=
369 (curr_recv_count - i2c_bus->fifo_depth))
370 ;
371 /*
372 * Check number of bytes to be received against maximum
373 * transfer size and update register accordingly.
374 */
375 if ((recv_count - i2c_bus->fifo_depth) >
376 CDNS_I2C_TRANSFER_SIZE) {
377 writel(CDNS_I2C_TRANSFER_SIZE,
378 ®s->transfer_size);
379 curr_recv_count = CDNS_I2C_TRANSFER_SIZE +
380 i2c_bus->fifo_depth;
381 } else {
382 writel(recv_count - i2c_bus->fifo_depth,
383 ®s->transfer_size);
384 curr_recv_count = recv_count;
385 }
386 } else if (recv_count && !hold_quirk && !curr_recv_count) {
387 if (recv_count > CDNS_I2C_TRANSFER_SIZE) {
388 writel(CDNS_I2C_TRANSFER_SIZE,
389 ®s->transfer_size);
390 curr_recv_count = CDNS_I2C_TRANSFER_SIZE;
391 } else {
392 writel(recv_count, ®s->transfer_size);
393 curr_recv_count = recv_count;
394 }
395 writel(addr, ®s->address);
396 }
397 }
398
399 /* Wait for the address and data to be sent */
400 ret = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
401 CDNS_I2C_INTERRUPT_ARBLOST);
402 if (!(ret & (CDNS_I2C_INTERRUPT_ARBLOST |
403 CDNS_I2C_INTERRUPT_COMP)))
404 return -ETIMEDOUT;
405 if (ret & CDNS_I2C_INTERRUPT_ARBLOST)
406 return -EAGAIN;
407
408 return 0;
409 }
410
cdns_i2c_xfer(struct udevice * dev,struct i2c_msg * msg,int nmsgs)411 static int cdns_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
412 int nmsgs)
413 {
414 struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
415 int ret = 0;
416 int count;
417 bool hold_quirk;
418 struct i2c_msg *message = msg;
419 int num_msgs = nmsgs;
420
421 hold_quirk = !!(i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT);
422
423 if (nmsgs > 1) {
424 /*
425 * This controller does not give completion interrupt after a
426 * master receive message if HOLD bit is set (repeated start),
427 * resulting in SW timeout. Hence, if a receive message is
428 * followed by any other message, an error is returned
429 * indicating that this sequence is not supported.
430 */
431 for (count = 0; (count < nmsgs - 1) && hold_quirk; count++) {
432 if (msg[count].flags & I2C_M_RD) {
433 printf("Can't do repeated start after a receive message\n");
434 return -EOPNOTSUPP;
435 }
436 }
437
438 i2c_bus->hold_flag = 1;
439 setbits_le32(&i2c_bus->regs->control, CDNS_I2C_CONTROL_HOLD);
440 } else {
441 i2c_bus->hold_flag = 0;
442 }
443
444 debug("i2c_xfer: %d messages\n", nmsgs);
445 for (u8 retry = 0; retry < CDNS_I2C_ARB_LOST_MAX_RETRIES &&
446 nmsgs > 0;) {
447 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
448 if (msg->flags & I2C_M_RD) {
449 ret = cdns_i2c_read_data(i2c_bus, msg->addr, msg->buf,
450 msg->len);
451 } else {
452 ret = cdns_i2c_write_data(i2c_bus, msg->addr, msg->buf,
453 msg->len);
454 }
455 if (ret == -EAGAIN) {
456 msg = message;
457 nmsgs = num_msgs;
458 retry++;
459 printf("%s,arbitration lost, retrying:%d\n", __func__,
460 retry);
461 continue;
462 }
463 nmsgs--;
464 msg++;
465 if (ret) {
466 debug("i2c_write: error sending\n");
467 return -EREMOTEIO;
468 }
469 }
470
471 return ret;
472 }
473
cdns_i2c_of_to_plat(struct udevice * dev)474 static int cdns_i2c_of_to_plat(struct udevice *dev)
475 {
476 struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
477 struct cdns_i2c_platform_data *pdata =
478 (struct cdns_i2c_platform_data *)dev_get_driver_data(dev);
479 struct clk clk;
480 int ret;
481
482 i2c_bus->regs = dev_read_addr_ptr(dev);
483 if (!i2c_bus->regs)
484 return -EINVAL;
485
486 if (pdata)
487 i2c_bus->quirks = pdata->quirks;
488
489 ret = clk_get_by_index(dev, 0, &clk);
490 if (ret)
491 return ret;
492
493 i2c_bus->input_freq = clk_get_rate(&clk);
494
495 ret = clk_enable(&clk);
496 if (ret) {
497 dev_err(dev, "failed to enable clock\n");
498 return ret;
499 }
500
501 /* Update FIFO depth based on device tree entry */
502 i2c_bus->fifo_depth = dev_read_u32_default(dev, "fifo-depth",
503 CDNS_I2C_FIFO_DEPTH_DEFAULT);
504
505 return 0;
506 }
507
508 static const struct dm_i2c_ops cdns_i2c_ops = {
509 .xfer = cdns_i2c_xfer,
510 .set_bus_speed = cdns_i2c_set_bus_speed,
511 };
512
513 static const struct cdns_i2c_platform_data r1p10_i2c_def = {
514 .quirks = CDNS_I2C_BROKEN_HOLD_BIT,
515 };
516
517 static const struct udevice_id cdns_i2c_of_match[] = {
518 { .compatible = "cdns,i2c-r1p10", .data = (ulong)&r1p10_i2c_def },
519 { .compatible = "cdns,i2c-r1p14" },
520 { /* end of table */ }
521 };
522
523 U_BOOT_DRIVER(cdns_i2c) = {
524 .name = "i2c_cdns",
525 .id = UCLASS_I2C,
526 .of_match = cdns_i2c_of_match,
527 .of_to_plat = cdns_i2c_of_to_plat,
528 .priv_auto = sizeof(struct i2c_cdns_bus),
529 .ops = &cdns_i2c_ops,
530 };
531