1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Microchip I2C controller driver
4 *
5 * Copyright (C) 2021-2022 Microchip Technology Inc.
6 * Padmarao Begari <padmarao.begari@microchip.com>
7 * Conor Dooley <conor.dooley@microchip.com>
8 */
9 #include <clk.h>
10 #include <dm.h>
11 #include <i2c.h>
12 #include <asm/io.h>
13 #include <dm/device_compat.h>
14 #include <linux/bitops.h>
15 #include <linux/delay.h>
16 #include <linux/err.h>
17
18 #define MICROCHIP_I2C_TIMEOUT (1000 * 60)
19
20 #define MPFS_I2C_CTRL (0x00)
21 #define CTRL_CR0 (0x00)
22 #define CTRL_CR1 (0x01)
23 #define CTRL_AA BIT(2)
24 #define CTRL_SI BIT(3)
25 #define CTRL_STO BIT(4)
26 #define CTRL_STA BIT(5)
27 #define CTRL_ENS1 BIT(6)
28 #define CTRL_CR2 (0x07)
29 #define MPFS_I2C_STATUS (0x04)
30 #define STATUS_BUS_ERROR (0x00)
31 #define STATUS_M_START_SENT (0x08)
32 #define STATUS_M_REPEATED_START_SENT (0x10)
33 #define STATUS_M_SLAW_ACK (0x18)
34 #define STATUS_M_SLAW_NACK (0x20)
35 #define STATUS_M_TX_DATA_ACK (0x28)
36 #define STATUS_M_TX_DATA_NACK (0x30)
37 #define STATUS_M_ARB_LOST (0x38)
38 #define STATUS_M_SLAR_ACK (0x40)
39 #define STATUS_M_SLAR_NACK (0x48)
40 #define STATUS_M_RX_DATA_ACKED (0x50)
41 #define STATUS_M_RX_DATA_NACKED (0x58)
42 #define STATUS_S_SLAW_ACKED (0x60)
43 #define STATUS_S_ARB_LOST_SLAW_ACKED (0x68)
44 #define STATUS_S_GENERAL_CALL_ACKED (0x70)
45 #define STATUS_S_ARB_LOST_GENERAL_CALL_ACKED (0x78)
46 #define STATUS_S_RX_DATA_ACKED (0x80)
47 #define STATUS_S_RX_DATA_NACKED (0x88)
48 #define STATUS_S_GENERAL_CALL_RX_DATA_ACKED (0x90)
49 #define STATUS_S_GENERAL_CALL_RX_DATA_NACKED (0x98)
50 #define STATUS_S_RX_STOP (0xA0)
51 #define STATUS_S_SLAR_ACKED (0xA8)
52 #define STATUS_S_ARB_LOST_SLAR_ACKED (0xB0)
53 #define STATUS_S_TX_DATA_ACK (0xb8)
54 #define STATUS_S_TX_DATA_NACK (0xC0)
55 #define STATUS_LAST_DATA_ACK (0xC8)
56 #define STATUS_M_SMB_MASTER_RESET (0xD0)
57 #define STATUS_S_SCL_LOW_TIMEOUT (0xD8)
58 #define STATUS_NO_STATE_INFO (0xF8)
59 #define MPFS_I2C_DATA (0x08)
60 #define MPFS_I2C_SLAVE0_ADDR (0x0c)
61 #define MPFS_I2C_SMBUS (0x10)
62 #define MPFS_I2C_FREQ (0x14)
63 #define MPFS_I2C_GLITCHREG (0x18)
64 #define MPFS_I2C_SLAVE1_ADDR (0x1c)
65
66 #define PCLK_DIV_256 ((0 << CTRL_CR0) | (0 << CTRL_CR1) | (0 << CTRL_CR2))
67 #define PCLK_DIV_224 ((1 << CTRL_CR0) | (0 << CTRL_CR1) | (0 << CTRL_CR2))
68 #define PCLK_DIV_192 ((0 << CTRL_CR0) | (1 << CTRL_CR1) | (0 << CTRL_CR2))
69 #define PCLK_DIV_160 ((1 << CTRL_CR0) | (1 << CTRL_CR1) | (0 << CTRL_CR2))
70 #define PCLK_DIV_960 ((0 << CTRL_CR0) | (0 << CTRL_CR1) | (1 << CTRL_CR2))
71 #define PCLK_DIV_120 ((1 << CTRL_CR0) | (0 << CTRL_CR1) | (1 << CTRL_CR2))
72 #define PCLK_DIV_60 ((0 << CTRL_CR0) | (1 << CTRL_CR1) | (1 << CTRL_CR2))
73 #define BCLK_DIV_8 ((1 << CTRL_CR0) | (1 << CTRL_CR1) | (1 << CTRL_CR2))
74 #define CLK_MASK ((1 << CTRL_CR0) | (1 << CTRL_CR1) | (1 << CTRL_CR2))
75
76 /*
77 * mpfs_i2c_bus - I2C bus context
78 * @base: pointer to register struct
79 * @msg_len: number of bytes transferred in msg
80 * @msg_err: error code for completed message
81 * @i2c_clk: clock reference for i2c input clock
82 * @clk_rate: current i2c bus clock rate
83 * @buf: ptr to msg buffer for easier use.
84 * @addr: i2c address.
85 * @isr_status: cached copy of local ISR status.
86 */
87 struct mpfs_i2c_bus {
88 void __iomem *base;
89 size_t msg_len;
90 int msg_err;
91 struct clk i2c_clk;
92 u32 clk_rate;
93 u8 *buf;
94 u8 addr;
95 u32 isr_status;
96 };
97
i2c_8bit_addr_from_msg(const struct i2c_msg * msg)98 static inline u8 i2c_8bit_addr_from_msg(const struct i2c_msg *msg)
99 {
100 return (msg->addr << 1) | (msg->flags & I2C_M_RD ? 1 : 0);
101 }
102
mpfs_i2c_int_clear(struct mpfs_i2c_bus * bus)103 static void mpfs_i2c_int_clear(struct mpfs_i2c_bus *bus)
104 {
105 u8 ctrl = readl(bus->base + MPFS_I2C_CTRL);
106
107 ctrl &= ~CTRL_SI;
108 writel(ctrl, bus->base + MPFS_I2C_CTRL);
109 }
110
mpfs_i2c_core_disable(struct mpfs_i2c_bus * bus)111 static void mpfs_i2c_core_disable(struct mpfs_i2c_bus *bus)
112 {
113 u8 ctrl = readl(bus->base + MPFS_I2C_CTRL);
114
115 ctrl &= ~CTRL_ENS1;
116 writel(ctrl, bus->base + MPFS_I2C_CTRL);
117 }
118
mpfs_i2c_core_enable(struct mpfs_i2c_bus * bus)119 static void mpfs_i2c_core_enable(struct mpfs_i2c_bus *bus)
120 {
121 u8 ctrl = readl(bus->base + MPFS_I2C_CTRL);
122
123 ctrl |= CTRL_ENS1;
124 writel(ctrl, bus->base + MPFS_I2C_CTRL);
125 }
126
mpfs_i2c_reset(struct mpfs_i2c_bus * bus)127 static void mpfs_i2c_reset(struct mpfs_i2c_bus *bus)
128 {
129 mpfs_i2c_core_disable(bus);
130 mpfs_i2c_core_enable(bus);
131 }
132
mpfs_i2c_stop(struct mpfs_i2c_bus * bus)133 static inline void mpfs_i2c_stop(struct mpfs_i2c_bus *bus)
134 {
135 u8 ctrl = readl(bus->base + MPFS_I2C_CTRL);
136
137 ctrl |= CTRL_STO;
138 writel(ctrl, bus->base + MPFS_I2C_CTRL);
139 }
140
mpfs_generate_divisor(u32 rate,u8 * code)141 static inline int mpfs_generate_divisor(u32 rate, u8 *code)
142 {
143 int ret = 0;
144
145 if (rate >= 960)
146 *code = PCLK_DIV_960;
147 else if (rate >= 256)
148 *code = PCLK_DIV_256;
149 else if (rate >= 224)
150 *code = PCLK_DIV_224;
151 else if (rate >= 192)
152 *code = PCLK_DIV_192;
153 else if (rate >= 160)
154 *code = PCLK_DIV_160;
155 else if (rate >= 120)
156 *code = PCLK_DIV_120;
157 else if (rate >= 60)
158 *code = PCLK_DIV_60;
159 else if (rate >= 8)
160 *code = BCLK_DIV_8;
161 else
162 ret = -EINVAL;
163
164 return ret;
165 }
166
mpfs_i2c_init(struct mpfs_i2c_bus * bus,struct udevice * dev)167 static int mpfs_i2c_init(struct mpfs_i2c_bus *bus, struct udevice *dev)
168 {
169 u32 clk_rate, divisor;
170 u8 clkval, ctrl;
171 int ret;
172
173 ret = clk_get_by_index(dev, 0, &bus->i2c_clk);
174 if (ret)
175 return -EINVAL;
176
177 ret = clk_enable(&bus->i2c_clk);
178 if (ret)
179 return ret;
180
181 clk_rate = clk_get_rate(&bus->i2c_clk);
182 if (!clk_rate)
183 return -EINVAL;
184
185 divisor = clk_rate / bus->clk_rate;
186
187 ctrl = readl(bus->base + MPFS_I2C_CTRL);
188
189 ctrl &= ~CLK_MASK;
190
191 ret = mpfs_generate_divisor(divisor, &clkval);
192 if (ret)
193 return -EINVAL;
194
195 ctrl |= clkval;
196
197 writel(ctrl, bus->base + MPFS_I2C_CTRL);
198
199 ctrl = readl(bus->base + MPFS_I2C_CTRL);
200
201 /* Reset I2C core */
202 mpfs_i2c_reset(bus);
203
204 return 0;
205 }
206
mpfs_i2c_transfer(struct mpfs_i2c_bus * bus,u32 data)207 static void mpfs_i2c_transfer(struct mpfs_i2c_bus *bus, u32 data)
208 {
209 if (bus->msg_len > 0)
210 writel(data, bus->base + MPFS_I2C_DATA);
211 }
212
mpfs_i2c_empty_rx(struct mpfs_i2c_bus * bus)213 static void mpfs_i2c_empty_rx(struct mpfs_i2c_bus *bus)
214 {
215 u8 ctrl;
216 u8 data_read;
217
218 if (bus->msg_len > 0) {
219 data_read = readl(bus->base + MPFS_I2C_DATA);
220 *bus->buf++ = data_read;
221 bus->msg_len--;
222 }
223
224 if (bus->msg_len <= 1) {
225 ctrl = readl(bus->base + MPFS_I2C_CTRL);
226 ctrl &= ~CTRL_AA;
227 writel(ctrl, bus->base + MPFS_I2C_CTRL);
228 }
229 }
230
mpfs_i2c_fill_tx(struct mpfs_i2c_bus * bus)231 static int mpfs_i2c_fill_tx(struct mpfs_i2c_bus *bus)
232 {
233 mpfs_i2c_transfer(bus, *bus->buf++);
234 bus->msg_len--;
235
236 return 0;
237 }
238
mpfs_i2c_service_handler(struct mpfs_i2c_bus * bus)239 static int mpfs_i2c_service_handler(struct mpfs_i2c_bus *bus)
240 {
241 bool finish = false;
242 u32 status;
243 u8 ctrl;
244
245 status = bus->isr_status;
246
247 switch (status) {
248 case STATUS_M_START_SENT:
249 case STATUS_M_REPEATED_START_SENT:
250 ctrl = readl(bus->base + MPFS_I2C_CTRL);
251 ctrl &= ~CTRL_STA;
252 writel(bus->addr, bus->base + MPFS_I2C_DATA);
253 writel(ctrl, bus->base + MPFS_I2C_CTRL);
254 break;
255 case STATUS_M_SLAW_ACK:
256 case STATUS_M_TX_DATA_ACK:
257 if (bus->msg_len > 0) {
258 mpfs_i2c_fill_tx(bus);
259 } else {
260 /* On the last byte to be transmitted, send STOP */
261 mpfs_i2c_stop(bus);
262 finish = true;
263 }
264 break;
265 case STATUS_M_SLAR_ACK:
266 if (bus->msg_len > 1u) {
267 ctrl = readl(bus->base + MPFS_I2C_CTRL);
268 ctrl |= CTRL_AA;
269 writel(ctrl, bus->base + MPFS_I2C_CTRL);
270 } else if (bus->msg_len == 1u) {
271 ctrl = readl(bus->base + MPFS_I2C_CTRL);
272 ctrl &= ~CTRL_AA;
273 writel(ctrl, bus->base + MPFS_I2C_CTRL);
274 } else {
275 ctrl = readl(bus->base + MPFS_I2C_CTRL);
276 ctrl |= CTRL_AA;
277 writel(ctrl, bus->base + MPFS_I2C_CTRL);
278 /* On the last byte to be transmitted, send STOP */
279 mpfs_i2c_stop(bus);
280 finish = true;
281 }
282 break;
283 case STATUS_M_RX_DATA_ACKED:
284 mpfs_i2c_empty_rx(bus);
285 break;
286 case STATUS_M_RX_DATA_NACKED:
287 mpfs_i2c_empty_rx(bus);
288 if (bus->msg_len == 0) {
289 /* On the last byte to be transmitted, send STOP */
290 mpfs_i2c_stop(bus);
291 finish = true;
292 }
293 break;
294 case STATUS_M_TX_DATA_NACK:
295 case STATUS_M_SLAR_NACK:
296 case STATUS_M_SLAW_NACK:
297 bus->msg_err = -ENXIO;
298 mpfs_i2c_stop(bus);
299 finish = true;
300 break;
301
302 case STATUS_M_ARB_LOST:
303 /* Handle Lost Arbitration */
304 bus->msg_err = -EAGAIN;
305 finish = true;
306 break;
307 default:
308 break;
309 }
310
311 if (finish) {
312 ctrl = readl(bus->base + MPFS_I2C_CTRL);
313 ctrl &= ~CTRL_AA;
314 writel(ctrl, bus->base + MPFS_I2C_CTRL);
315 return 0;
316 }
317
318 return 1;
319 }
320
mpfs_i2c_service(struct mpfs_i2c_bus * bus)321 static int mpfs_i2c_service(struct mpfs_i2c_bus *bus)
322 {
323 int ret = 0;
324 int si_bit;
325
326 si_bit = readl(bus->base + MPFS_I2C_CTRL);
327 if (si_bit & CTRL_SI) {
328 bus->isr_status = readl(bus->base + MPFS_I2C_STATUS);
329 ret = mpfs_i2c_service_handler(bus);
330 }
331 /* Clear the si flag */
332 mpfs_i2c_int_clear(bus);
333 si_bit = readl(bus->base + MPFS_I2C_CTRL);
334
335 return ret;
336 }
337
mpfs_i2c_check_service_change(struct mpfs_i2c_bus * bus)338 static int mpfs_i2c_check_service_change(struct mpfs_i2c_bus *bus)
339 {
340 u8 ctrl;
341 u32 count = 0;
342
343 while (1) {
344 ctrl = readl(bus->base + MPFS_I2C_CTRL);
345 if (ctrl & CTRL_SI)
346 break;
347 udelay(1);
348 count += 1;
349 if (count == MICROCHIP_I2C_TIMEOUT)
350 return -ETIMEDOUT;
351 }
352 return 0;
353 }
354
mpfs_i2c_poll_device(struct mpfs_i2c_bus * bus)355 static int mpfs_i2c_poll_device(struct mpfs_i2c_bus *bus)
356 {
357 int ret;
358
359 while (1) {
360 ret = mpfs_i2c_check_service_change(bus);
361 if (ret)
362 return ret;
363
364 ret = mpfs_i2c_service(bus);
365 if (!ret)
366 /* all messages have been transferred */
367 return ret;
368 }
369 }
370
mpfs_i2c_xfer_msg(struct mpfs_i2c_bus * bus,struct i2c_msg * msg)371 static int mpfs_i2c_xfer_msg(struct mpfs_i2c_bus *bus, struct i2c_msg *msg)
372 {
373 u8 ctrl;
374 int ret;
375
376 if (!msg->len || !msg->buf)
377 return -EINVAL;
378
379 bus->addr = i2c_8bit_addr_from_msg(msg);
380 bus->msg_len = msg->len;
381 bus->buf = msg->buf;
382 bus->msg_err = 0;
383
384 mpfs_i2c_core_enable(bus);
385
386 ctrl = readl(bus->base + MPFS_I2C_CTRL);
387
388 ctrl |= CTRL_STA;
389
390 writel(ctrl, bus->base + MPFS_I2C_CTRL);
391
392 ret = mpfs_i2c_poll_device(bus);
393 if (ret)
394 return ret;
395
396 return bus->msg_err;
397 }
398
mpfs_i2c_xfer(struct udevice * dev,struct i2c_msg * msgs,int num_msgs)399 static int mpfs_i2c_xfer(struct udevice *dev, struct i2c_msg *msgs, int num_msgs)
400 {
401 struct mpfs_i2c_bus *bus = dev_get_priv(dev);
402 int idx, ret;
403
404 if (!msgs || !num_msgs)
405 return -EINVAL;
406
407 for (idx = 0; idx < num_msgs; idx++) {
408 ret = mpfs_i2c_xfer_msg(bus, msgs++);
409 if (ret)
410 return ret;
411 }
412
413 return ret;
414 }
415
mpfs_i2c_probe_chip(struct udevice * dev,uint addr,uint flags)416 static int mpfs_i2c_probe_chip(struct udevice *dev, uint addr, uint flags)
417 {
418 struct mpfs_i2c_bus *bus = dev_get_priv(dev);
419 int ret;
420 u8 ctrl, reg = 0;
421
422 /*
423 * Send the chip address and verify that the
424 * address was <ACK>ed.
425 */
426 bus->addr = addr << 1 | I2C_M_RD;
427 bus->buf = ®
428 bus->msg_len = 0;
429 bus->msg_err = 0;
430
431 mpfs_i2c_core_enable(bus);
432
433 ctrl = readl(bus->base + MPFS_I2C_CTRL);
434
435 ctrl |= CTRL_STA;
436
437 writel(ctrl, bus->base + MPFS_I2C_CTRL);
438
439 ret = mpfs_i2c_poll_device(bus);
440 if (ret)
441 return ret;
442
443 return bus->msg_err;
444 }
445
mpfs_i2c_probe(struct udevice * dev)446 static int mpfs_i2c_probe(struct udevice *dev)
447 {
448 int ret;
449 u32 val;
450 struct mpfs_i2c_bus *bus = dev_get_priv(dev);
451
452 bus->base = dev_read_addr_ptr(dev);
453 if (!bus->base)
454 return -EINVAL;
455
456 val = dev_read_u32(dev, "clock-frequency", &bus->clk_rate);
457 if (val) {
458 printf("Default to 100kHz\n");
459 /* default clock rate */
460 bus->clk_rate = 100000;
461 }
462
463 if (bus->clk_rate > 400000 || bus->clk_rate <= 0) {
464 printf("Invalid clock-frequency %d\n", bus->clk_rate);
465 return -EINVAL;
466 }
467
468 ret = mpfs_i2c_init(bus, dev);
469
470 return ret;
471 }
472
473 static const struct dm_i2c_ops mpfs_i2c_ops = {
474 .xfer = mpfs_i2c_xfer,
475 .probe_chip = mpfs_i2c_probe_chip,
476 };
477
478 static const struct udevice_id mpfs_i2c_ids[] = {
479 {.compatible = "microchip,mpfs-i2c"},
480 {}
481 };
482
483 U_BOOT_DRIVER(mpfs_i2c) = {
484 .name = "mpfs_i2c",
485 .id = UCLASS_I2C,
486 .of_match = mpfs_i2c_ids,
487 .ops = &mpfs_i2c_ops,
488 .probe = mpfs_i2c_probe,
489 .priv_auto = sizeof(struct mpfs_i2c_bus),
490 };
491