1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2000
4 * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
5 *
6 * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * (C) Copyright 2003 Pengutronix e.K.
10 * Robert Schwebel <r.schwebel@pengutronix.de>
11 *
12 * (C) Copyright 2011 Marvell Inc.
13 * Lei Wen <leiwen@marvell.com>
14 *
15 * Back ported to the 8xx platform (from the 8260 platform) by
16 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
17 */
18
19 #include <dm.h>
20 #include <i2c.h>
21 #include <log.h>
22 #include <asm/io.h>
23 #include <linux/delay.h>
24 #include "mv_i2c.h"
25
26 /* All transfers are described by this data structure */
27 struct mv_i2c_msg {
28 u8 condition;
29 u8 acknack;
30 u8 direction;
31 u8 data;
32 };
33
34 #ifdef CONFIG_ARMADA_3700
35 /* Armada 3700 has no padding between the registers */
36 struct mv_i2c {
37 u32 ibmr;
38 u32 idbr;
39 u32 icr;
40 u32 isr;
41 u32 isar;
42 };
43 #else
44 struct mv_i2c {
45 u32 ibmr;
46 u32 pad0;
47 u32 idbr;
48 u32 pad1;
49 u32 icr;
50 u32 pad2;
51 u32 isr;
52 u32 pad3;
53 u32 isar;
54 };
55 #endif
56
57 /*
58 * Dummy implementation that can be overwritten by a board
59 * specific function
60 */
i2c_clk_enable(void)61 __weak void i2c_clk_enable(void)
62 {
63 }
64
65 /*
66 * i2c_reset: - reset the host controller
67 *
68 */
i2c_reset(struct mv_i2c * base)69 static void i2c_reset(struct mv_i2c *base)
70 {
71 u32 icr_mode;
72
73 /* Save bus mode (standard or fast speed) for later use */
74 icr_mode = readl(&base->icr) & ICR_MODE_MASK;
75 writel(readl(&base->icr) & ~ICR_IUE, &base->icr); /* disable unit */
76 writel(readl(&base->icr) | ICR_UR, &base->icr); /* reset the unit */
77 udelay(100);
78 writel(readl(&base->icr) & ~ICR_IUE, &base->icr); /* disable unit */
79
80 i2c_clk_enable();
81
82 writel(0x0, &base->isar); /* set our slave address */
83 /* set control reg values */
84 writel(I2C_ICR_INIT | icr_mode, &base->icr);
85 writel(I2C_ISR_INIT, &base->isr); /* set clear interrupt bits */
86 writel(readl(&base->icr) | ICR_IUE, &base->icr); /* enable unit */
87 udelay(100);
88 }
89
90 /*
91 * i2c_isr_set_cleared: - wait until certain bits of the I2C status register
92 * are set and cleared
93 *
94 * @return: 1 in case of success, 0 means timeout (no match within 10 ms).
95 */
i2c_isr_set_cleared(struct mv_i2c * base,unsigned long set_mask,unsigned long cleared_mask)96 static int i2c_isr_set_cleared(struct mv_i2c *base, unsigned long set_mask,
97 unsigned long cleared_mask)
98 {
99 int timeout = 1000, isr;
100
101 do {
102 isr = readl(&base->isr);
103 udelay(10);
104 if (timeout-- < 0)
105 return 0;
106 } while (((isr & set_mask) != set_mask)
107 || ((isr & cleared_mask) != 0));
108
109 return 1;
110 }
111
112 /*
113 * i2c_transfer: - Transfer one byte over the i2c bus
114 *
115 * This function can tranfer a byte over the i2c bus in both directions.
116 * It is used by the public API functions.
117 *
118 * @return: 0: transfer successful
119 * -1: message is empty
120 * -2: transmit timeout
121 * -3: ACK missing
122 * -4: receive timeout
123 * -5: illegal parameters
124 * -6: bus is busy and couldn't be aquired
125 */
i2c_transfer(struct mv_i2c * base,struct mv_i2c_msg * msg)126 static int i2c_transfer(struct mv_i2c *base, struct mv_i2c_msg *msg)
127 {
128 int ret;
129
130 if (!msg)
131 goto transfer_error_msg_empty;
132
133 switch (msg->direction) {
134 case I2C_WRITE:
135 /* check if bus is not busy */
136 if (!i2c_isr_set_cleared(base, 0, ISR_IBB))
137 goto transfer_error_bus_busy;
138
139 /* start transmission */
140 writel(readl(&base->icr) & ~ICR_START, &base->icr);
141 writel(readl(&base->icr) & ~ICR_STOP, &base->icr);
142 writel(msg->data, &base->idbr);
143 if (msg->condition == I2C_COND_START)
144 writel(readl(&base->icr) | ICR_START, &base->icr);
145 if (msg->condition == I2C_COND_STOP)
146 writel(readl(&base->icr) | ICR_STOP, &base->icr);
147 if (msg->acknack == I2C_ACKNAK_SENDNAK)
148 writel(readl(&base->icr) | ICR_ACKNAK, &base->icr);
149 if (msg->acknack == I2C_ACKNAK_SENDACK)
150 writel(readl(&base->icr) & ~ICR_ACKNAK, &base->icr);
151 writel(readl(&base->icr) & ~ICR_ALDIE, &base->icr);
152 writel(readl(&base->icr) | ICR_TB, &base->icr);
153
154 /* transmit register empty? */
155 if (!i2c_isr_set_cleared(base, ISR_ITE, 0))
156 goto transfer_error_transmit_timeout;
157
158 /* clear 'transmit empty' state */
159 writel(readl(&base->isr) | ISR_ITE, &base->isr);
160
161 /* wait for ACK from slave */
162 if (msg->acknack == I2C_ACKNAK_WAITACK)
163 if (!i2c_isr_set_cleared(base, 0, ISR_ACKNAK))
164 goto transfer_error_ack_missing;
165 break;
166
167 case I2C_READ:
168
169 /* check if bus is not busy */
170 if (!i2c_isr_set_cleared(base, 0, ISR_IBB))
171 goto transfer_error_bus_busy;
172
173 /* start receive */
174 writel(readl(&base->icr) & ~ICR_START, &base->icr);
175 writel(readl(&base->icr) & ~ICR_STOP, &base->icr);
176 if (msg->condition == I2C_COND_START)
177 writel(readl(&base->icr) | ICR_START, &base->icr);
178 if (msg->condition == I2C_COND_STOP)
179 writel(readl(&base->icr) | ICR_STOP, &base->icr);
180 if (msg->acknack == I2C_ACKNAK_SENDNAK)
181 writel(readl(&base->icr) | ICR_ACKNAK, &base->icr);
182 if (msg->acknack == I2C_ACKNAK_SENDACK)
183 writel(readl(&base->icr) & ~ICR_ACKNAK, &base->icr);
184 writel(readl(&base->icr) & ~ICR_ALDIE, &base->icr);
185 writel(readl(&base->icr) | ICR_TB, &base->icr);
186
187 /* receive register full? */
188 if (!i2c_isr_set_cleared(base, ISR_IRF, 0))
189 goto transfer_error_receive_timeout;
190
191 msg->data = readl(&base->idbr);
192
193 /* clear 'receive empty' state */
194 writel(readl(&base->isr) | ISR_IRF, &base->isr);
195 break;
196 default:
197 goto transfer_error_illegal_param;
198 }
199
200 return 0;
201
202 transfer_error_msg_empty:
203 debug("i2c_transfer: error: 'msg' is empty\n");
204 ret = -1;
205 goto i2c_transfer_finish;
206
207 transfer_error_transmit_timeout:
208 debug("i2c_transfer: error: transmit timeout\n");
209 ret = -2;
210 goto i2c_transfer_finish;
211
212 transfer_error_ack_missing:
213 debug("i2c_transfer: error: ACK missing\n");
214 ret = -3;
215 goto i2c_transfer_finish;
216
217 transfer_error_receive_timeout:
218 debug("i2c_transfer: error: receive timeout\n");
219 ret = -4;
220 goto i2c_transfer_finish;
221
222 transfer_error_illegal_param:
223 debug("i2c_transfer: error: illegal parameters\n");
224 ret = -5;
225 goto i2c_transfer_finish;
226
227 transfer_error_bus_busy:
228 debug("i2c_transfer: error: bus is busy\n");
229 ret = -6;
230 goto i2c_transfer_finish;
231
232 i2c_transfer_finish:
233 debug("i2c_transfer: ISR: 0x%04x\n", readl(&base->isr));
234 i2c_reset(base);
235 return ret;
236 }
237
__i2c_read(struct mv_i2c * base,uchar chip,u8 * addr,int alen,uchar * buffer,int len)238 static int __i2c_read(struct mv_i2c *base, uchar chip, u8 *addr, int alen,
239 uchar *buffer, int len)
240 {
241 struct mv_i2c_msg msg;
242
243 debug("i2c_read(chip=0x%02x, addr=0x%02x, alen=0x%02x, "
244 "len=0x%02x)\n", chip, *addr, alen, len);
245
246 if (len == 0) {
247 printf("reading zero byte is invalid\n");
248 return -EINVAL;
249 }
250
251 i2c_reset(base);
252
253 /* dummy chip address write */
254 debug("i2c_read: dummy chip address write\n");
255 msg.condition = I2C_COND_START;
256 msg.acknack = I2C_ACKNAK_WAITACK;
257 msg.direction = I2C_WRITE;
258 msg.data = (chip << 1);
259 msg.data &= 0xFE;
260 if (i2c_transfer(base, &msg))
261 return -1;
262
263 /*
264 * send memory address bytes;
265 * alen defines how much bytes we have to send.
266 */
267 while (--alen >= 0) {
268 debug("i2c_read: send address byte %02x (alen=%d)\n",
269 *addr, alen);
270 msg.condition = I2C_COND_NORMAL;
271 msg.acknack = I2C_ACKNAK_WAITACK;
272 msg.direction = I2C_WRITE;
273 msg.data = addr[alen];
274 if (i2c_transfer(base, &msg))
275 return -1;
276 }
277
278 /* start read sequence */
279 debug("i2c_read: start read sequence\n");
280 msg.condition = I2C_COND_START;
281 msg.acknack = I2C_ACKNAK_WAITACK;
282 msg.direction = I2C_WRITE;
283 msg.data = (chip << 1);
284 msg.data |= 0x01;
285 if (i2c_transfer(base, &msg))
286 return -1;
287
288 /* read bytes; send NACK at last byte */
289 while (len--) {
290 if (len == 0) {
291 msg.condition = I2C_COND_STOP;
292 msg.acknack = I2C_ACKNAK_SENDNAK;
293 } else {
294 msg.condition = I2C_COND_NORMAL;
295 msg.acknack = I2C_ACKNAK_SENDACK;
296 }
297
298 msg.direction = I2C_READ;
299 msg.data = 0x00;
300 if (i2c_transfer(base, &msg))
301 return -1;
302
303 *buffer = msg.data;
304 debug("i2c_read: reading byte (%p)=0x%02x\n",
305 buffer, *buffer);
306 buffer++;
307 }
308
309 i2c_reset(base);
310
311 return 0;
312 }
313
__i2c_write(struct mv_i2c * base,uchar chip,u8 * addr,int alen,uchar * buffer,int len)314 static int __i2c_write(struct mv_i2c *base, uchar chip, u8 *addr, int alen,
315 uchar *buffer, int len)
316 {
317 struct mv_i2c_msg msg;
318
319 debug("i2c_write(chip=0x%02x, addr=0x%02x, alen=0x%02x, "
320 "len=0x%02x)\n", chip, *addr, alen, len);
321
322 i2c_reset(base);
323
324 /* chip address write */
325 debug("i2c_write: chip address write\n");
326 msg.condition = I2C_COND_START;
327 msg.acknack = I2C_ACKNAK_WAITACK;
328 msg.direction = I2C_WRITE;
329 msg.data = (chip << 1);
330 msg.data &= 0xFE;
331 if (i2c_transfer(base, &msg))
332 return -1;
333
334 /*
335 * send memory address bytes;
336 * alen defines how much bytes we have to send.
337 */
338 while (--alen >= 0) {
339 debug("i2c_read: send address byte %02x (alen=%d)\n",
340 *addr, alen);
341 msg.condition = I2C_COND_NORMAL;
342 msg.acknack = I2C_ACKNAK_WAITACK;
343 msg.direction = I2C_WRITE;
344 msg.data = addr[alen];
345 if (i2c_transfer(base, &msg))
346 return -1;
347 }
348
349 /* write bytes; send NACK at last byte */
350 while (len--) {
351 debug("i2c_write: writing byte (%p)=0x%02x\n",
352 buffer, *buffer);
353
354 if (len == 0)
355 msg.condition = I2C_COND_STOP;
356 else
357 msg.condition = I2C_COND_NORMAL;
358
359 msg.acknack = I2C_ACKNAK_WAITACK;
360 msg.direction = I2C_WRITE;
361 msg.data = *(buffer++);
362
363 if (i2c_transfer(base, &msg))
364 return -1;
365 }
366
367 i2c_reset(base);
368
369 return 0;
370 }
371
372 #if !CONFIG_IS_ENABLED(DM_I2C)
373
374 static struct mv_i2c *base_glob;
375
376 /* API Functions */
i2c_init(int speed,int slaveaddr)377 void i2c_init(int speed, int slaveaddr)
378 {
379 u32 val;
380
381 base_glob = (struct mv_i2c *)CONFIG_MV_I2C_REG;
382
383 if (speed > I2C_SPEED_STANDARD_RATE)
384 val = ICR_FM;
385 else
386 val = ICR_SM;
387 clrsetbits_le32(&base_glob->icr, ICR_MODE_MASK, val);
388 }
389
__i2c_probe_chip(struct mv_i2c * base,uchar chip)390 static int __i2c_probe_chip(struct mv_i2c *base, uchar chip)
391 {
392 struct mv_i2c_msg msg;
393
394 i2c_reset(base);
395
396 msg.condition = I2C_COND_START;
397 msg.acknack = I2C_ACKNAK_WAITACK;
398 msg.direction = I2C_WRITE;
399 msg.data = (chip << 1) + 1;
400 if (i2c_transfer(base, &msg))
401 return -1;
402
403 msg.condition = I2C_COND_STOP;
404 msg.acknack = I2C_ACKNAK_SENDNAK;
405 msg.direction = I2C_READ;
406 msg.data = 0x00;
407 if (i2c_transfer(base, &msg))
408 return -1;
409
410 return 0;
411 }
412
413 /*
414 * i2c_probe: - Test if a chip answers for a given i2c address
415 *
416 * @chip: address of the chip which is searched for
417 * @return: 0 if a chip was found, -1 otherwhise
418 */
i2c_probe(uchar chip)419 int i2c_probe(uchar chip)
420 {
421 return __i2c_probe_chip(base_glob, chip);
422 }
423
424 /*
425 * i2c_read: - Read multiple bytes from an i2c device
426 *
427 * The higher level routines take into account that this function is only
428 * called with len < page length of the device (see configuration file)
429 *
430 * @chip: address of the chip which is to be read
431 * @addr: i2c data address within the chip
432 * @alen: length of the i2c data address (1..2 bytes)
433 * @buffer: where to write the data
434 * @len: how much byte do we want to read
435 * @return: 0 in case of success
436 */
i2c_read(uchar chip,uint addr,int alen,uchar * buffer,int len)437 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
438 {
439 u8 addr_bytes[4];
440
441 addr_bytes[0] = (addr >> 0) & 0xFF;
442 addr_bytes[1] = (addr >> 8) & 0xFF;
443 addr_bytes[2] = (addr >> 16) & 0xFF;
444 addr_bytes[3] = (addr >> 24) & 0xFF;
445
446 return __i2c_read(base_glob, chip, addr_bytes, alen, buffer, len);
447 }
448
449 /*
450 * i2c_write: - Write multiple bytes to an i2c device
451 *
452 * The higher level routines take into account that this function is only
453 * called with len < page length of the device (see configuration file)
454 *
455 * @chip: address of the chip which is to be written
456 * @addr: i2c data address within the chip
457 * @alen: length of the i2c data address (1..2 bytes)
458 * @buffer: where to find the data to be written
459 * @len: how much byte do we want to read
460 * @return: 0 in case of success
461 */
i2c_write(uchar chip,uint addr,int alen,uchar * buffer,int len)462 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
463 {
464 u8 addr_bytes[4];
465
466 addr_bytes[0] = (addr >> 0) & 0xFF;
467 addr_bytes[1] = (addr >> 8) & 0xFF;
468 addr_bytes[2] = (addr >> 16) & 0xFF;
469 addr_bytes[3] = (addr >> 24) & 0xFF;
470
471 return __i2c_write(base_glob, chip, addr_bytes, alen, buffer, len);
472 }
473
474 #else /* CONFIG_DM_I2C */
475
476 struct mv_i2c_priv {
477 struct mv_i2c *base;
478 };
479
mv_i2c_xfer(struct udevice * bus,struct i2c_msg * msg,int nmsgs)480 static int mv_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
481 {
482 struct mv_i2c_priv *i2c = dev_get_priv(bus);
483 struct i2c_msg *dmsg, *omsg, dummy;
484
485 memset(&dummy, 0, sizeof(struct i2c_msg));
486
487 /*
488 * We expect either two messages (one with an offset and one with the
489 * actual data) or one message (just data or offset/data combined)
490 */
491 if (nmsgs > 2 || nmsgs == 0) {
492 debug("%s: Only one or two messages are supported.", __func__);
493 return -1;
494 }
495
496 omsg = nmsgs == 1 ? &dummy : msg;
497 dmsg = nmsgs == 1 ? msg : msg + 1;
498
499 if (dmsg->flags & I2C_M_RD)
500 return __i2c_read(i2c->base, dmsg->addr, omsg->buf,
501 omsg->len, dmsg->buf, dmsg->len);
502 else
503 return __i2c_write(i2c->base, dmsg->addr, omsg->buf,
504 omsg->len, dmsg->buf, dmsg->len);
505 }
506
mv_i2c_set_bus_speed(struct udevice * bus,unsigned int speed)507 static int mv_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
508 {
509 struct mv_i2c_priv *priv = dev_get_priv(bus);
510 u32 val;
511
512 if (speed > I2C_SPEED_STANDARD_RATE)
513 val = ICR_FM;
514 else
515 val = ICR_SM;
516 clrsetbits_le32(&priv->base->icr, ICR_MODE_MASK, val);
517
518 return 0;
519 }
520
mv_i2c_probe(struct udevice * bus)521 static int mv_i2c_probe(struct udevice *bus)
522 {
523 struct mv_i2c_priv *priv = dev_get_priv(bus);
524
525 priv->base = dev_read_addr_ptr(bus);
526
527 return 0;
528 }
529
530 static const struct dm_i2c_ops mv_i2c_ops = {
531 .xfer = mv_i2c_xfer,
532 .set_bus_speed = mv_i2c_set_bus_speed,
533 };
534
535 static const struct udevice_id mv_i2c_ids[] = {
536 { .compatible = "marvell,armada-3700-i2c" },
537 { }
538 };
539
540 U_BOOT_DRIVER(i2c_mv) = {
541 .name = "i2c_mv",
542 .id = UCLASS_I2C,
543 .of_match = mv_i2c_ids,
544 .probe = mv_i2c_probe,
545 .priv_auto = sizeof(struct mv_i2c_priv),
546 .ops = &mv_i2c_ops,
547 };
548 #endif /* CONFIG_DM_I2C */
549