1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2011, 2013 Renesas Solutions Corp.
4 * Copyright (C) 2011, 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
5 *
6 * NOTE: This driver should be converted to driver model before June 2017.
7 * Please see doc/driver-model/i2c-howto.rst for instructions.
8 */
9
10 #include <i2c.h>
11 #include <log.h>
12 #include <asm/global_data.h>
13 #include <asm/io.h>
14 #include <linux/delay.h>
15
16 DECLARE_GLOBAL_DATA_PTR;
17
18 /* Every register is 32bit aligned, but only 8bits in size */
19 #define ureg(name) u8 name; u8 __pad_##name##0; u16 __pad_##name##1;
20 struct sh_i2c {
21 ureg(icdr);
22 ureg(iccr);
23 ureg(icsr);
24 ureg(icic);
25 ureg(iccl);
26 ureg(icch);
27 };
28 #undef ureg
29
30 /* ICCR */
31 #define SH_I2C_ICCR_ICE (1 << 7)
32 #define SH_I2C_ICCR_RACK (1 << 6)
33 #define SH_I2C_ICCR_RTS (1 << 4)
34 #define SH_I2C_ICCR_BUSY (1 << 2)
35 #define SH_I2C_ICCR_SCP (1 << 0)
36
37 /* ICSR / ICIC */
38 #define SH_IC_BUSY (1 << 4)
39 #define SH_IC_TACK (1 << 2)
40 #define SH_IC_WAIT (1 << 1)
41 #define SH_IC_DTE (1 << 0)
42
43 #ifdef CONFIG_SH_I2C_8BIT
44 /* store 8th bit of iccl and icch in ICIC register */
45 #define SH_I2C_ICIC_ICCLB8 (1 << 7)
46 #define SH_I2C_ICIC_ICCHB8 (1 << 6)
47 #endif
48
49 static const struct sh_i2c *i2c_dev[CONFIG_SYS_I2C_SH_NUM_CONTROLLERS] = {
50 (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE0,
51 #ifdef CONFIG_SYS_I2C_SH_BASE1
52 (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE1,
53 #endif
54 #ifdef CONFIG_SYS_I2C_SH_BASE2
55 (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE2,
56 #endif
57 #ifdef CONFIG_SYS_I2C_SH_BASE3
58 (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE3,
59 #endif
60 #ifdef CONFIG_SYS_I2C_SH_BASE4
61 (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE4,
62 #endif
63 };
64
65 static u16 iccl, icch;
66
67 #define IRQ_WAIT 1000
68
sh_irq_dte(struct sh_i2c * dev)69 static void sh_irq_dte(struct sh_i2c *dev)
70 {
71 int i;
72
73 for (i = 0; i < IRQ_WAIT; i++) {
74 if (SH_IC_DTE & readb(&dev->icsr))
75 break;
76 udelay(10);
77 }
78 }
79
sh_irq_dte_with_tack(struct sh_i2c * dev)80 static int sh_irq_dte_with_tack(struct sh_i2c *dev)
81 {
82 int i;
83
84 for (i = 0; i < IRQ_WAIT; i++) {
85 if (SH_IC_DTE & readb(&dev->icsr))
86 break;
87 if (SH_IC_TACK & readb(&dev->icsr))
88 return -1;
89 udelay(10);
90 }
91 return 0;
92 }
93
sh_irq_busy(struct sh_i2c * dev)94 static void sh_irq_busy(struct sh_i2c *dev)
95 {
96 int i;
97
98 for (i = 0; i < IRQ_WAIT; i++) {
99 if (!(SH_IC_BUSY & readb(&dev->icsr)))
100 break;
101 udelay(10);
102 }
103 }
104
sh_i2c_set_addr(struct sh_i2c * dev,u8 chip,u8 addr,int stop)105 static int sh_i2c_set_addr(struct sh_i2c *dev, u8 chip, u8 addr, int stop)
106 {
107 u8 icic = SH_IC_TACK;
108
109 debug("%s: chip: %x, addr: %x iccl: %x, icch %x\n",
110 __func__, chip, addr, iccl, icch);
111 clrbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
112 setbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
113
114 writeb(iccl & 0xff, &dev->iccl);
115 writeb(icch & 0xff, &dev->icch);
116 #ifdef CONFIG_SH_I2C_8BIT
117 if (iccl > 0xff)
118 icic |= SH_I2C_ICIC_ICCLB8;
119 if (icch > 0xff)
120 icic |= SH_I2C_ICIC_ICCHB8;
121 #endif
122 writeb(icic, &dev->icic);
123
124 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &dev->iccr);
125 sh_irq_dte(dev);
126
127 clrbits_8(&dev->icsr, SH_IC_TACK);
128 writeb(chip << 1, &dev->icdr);
129 if (sh_irq_dte_with_tack(dev) != 0)
130 return -1;
131
132 writeb(addr, &dev->icdr);
133 if (stop)
134 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS), &dev->iccr);
135
136 if (sh_irq_dte_with_tack(dev) != 0)
137 return -1;
138 return 0;
139 }
140
sh_i2c_finish(struct sh_i2c * dev)141 static void sh_i2c_finish(struct sh_i2c *dev)
142 {
143 writeb(0, &dev->icsr);
144 clrbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
145 }
146
147 static int
sh_i2c_raw_write(struct sh_i2c * dev,u8 chip,uint addr,u8 val)148 sh_i2c_raw_write(struct sh_i2c *dev, u8 chip, uint addr, u8 val)
149 {
150 int ret = -1;
151 if (sh_i2c_set_addr(dev, chip, addr, 0) != 0)
152 goto exit0;
153 udelay(10);
154
155 writeb(val, &dev->icdr);
156 if (sh_irq_dte_with_tack(dev) != 0)
157 goto exit0;
158
159 writeb((SH_I2C_ICCR_ICE | SH_I2C_ICCR_RTS), &dev->iccr);
160 if (sh_irq_dte_with_tack(dev) != 0)
161 goto exit0;
162 sh_irq_busy(dev);
163 ret = 0;
164
165 exit0:
166 sh_i2c_finish(dev);
167 return ret;
168 }
169
sh_i2c_raw_read(struct sh_i2c * dev,u8 chip,u8 addr)170 static int sh_i2c_raw_read(struct sh_i2c *dev, u8 chip, u8 addr)
171 {
172 int ret = -1;
173
174 if (sh_i2c_set_addr(dev, chip, addr, 1) != 0)
175 goto exit0;
176 udelay(100);
177
178 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &dev->iccr);
179 sh_irq_dte(dev);
180
181 writeb(chip << 1 | 0x01, &dev->icdr);
182 if (sh_irq_dte_with_tack(dev) != 0)
183 goto exit0;
184
185 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_SCP), &dev->iccr);
186 if (sh_irq_dte_with_tack(dev) != 0)
187 goto exit0;
188
189 ret = readb(&dev->icdr) & 0xff;
190
191 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RACK), &dev->iccr);
192 readb(&dev->icdr); /* Dummy read */
193 sh_irq_busy(dev);
194
195 exit0:
196 sh_i2c_finish(dev);
197
198 return ret;
199 }
200
201 static void
sh_i2c_init(struct i2c_adapter * adap,int speed,int slaveadd)202 sh_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
203 {
204 int num, denom, tmp;
205
206 /* No i2c support prior to relocation */
207 if (!(gd->flags & GD_FLG_RELOC))
208 return;
209
210 /*
211 * Calculate the value for iccl. From the data sheet:
212 * iccl = (p-clock / transfer-rate) * (L / (L + H))
213 * where L and H are the SCL low and high ratio.
214 */
215 num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_LOW;
216 denom = speed * (CONFIG_SH_I2C_DATA_HIGH + CONFIG_SH_I2C_DATA_LOW);
217 tmp = num * 10 / denom;
218 if (tmp % 10 >= 5)
219 iccl = (u16)((num/denom) + 1);
220 else
221 iccl = (u16)(num/denom);
222
223 /* Calculate the value for icch. From the data sheet:
224 icch = (p clock / transfer rate) * (H / (L + H)) */
225 num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_HIGH;
226 tmp = num * 10 / denom;
227 if (tmp % 10 >= 5)
228 icch = (u16)((num/denom) + 1);
229 else
230 icch = (u16)(num/denom);
231
232 debug("clock: %d, speed %d, iccl: %x, icch: %x\n",
233 CONFIG_SH_I2C_CLOCK, speed, iccl, icch);
234 }
235
sh_i2c_read(struct i2c_adapter * adap,uint8_t chip,uint addr,int alen,u8 * data,int len)236 static int sh_i2c_read(struct i2c_adapter *adap, uint8_t chip,
237 uint addr, int alen, u8 *data, int len)
238 {
239 int ret, i;
240 struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];
241
242 for (i = 0; i < len; i++) {
243 ret = sh_i2c_raw_read(dev, chip, addr + i);
244 if (ret < 0)
245 return -1;
246
247 data[i] = ret & 0xff;
248 debug("%s: data[%d]: %02x\n", __func__, i, data[i]);
249 }
250
251 return 0;
252 }
253
sh_i2c_write(struct i2c_adapter * adap,uint8_t chip,uint addr,int alen,u8 * data,int len)254 static int sh_i2c_write(struct i2c_adapter *adap, uint8_t chip, uint addr,
255 int alen, u8 *data, int len)
256 {
257 struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];
258 int i;
259
260 for (i = 0; i < len; i++) {
261 debug("%s: data[%d]: %02x\n", __func__, i, data[i]);
262 if (sh_i2c_raw_write(dev, chip, addr + i, data[i]) != 0)
263 return -1;
264 }
265 return 0;
266 }
267
268 static int
sh_i2c_probe(struct i2c_adapter * adap,u8 dev)269 sh_i2c_probe(struct i2c_adapter *adap, u8 dev)
270 {
271 u8 dummy[1];
272
273 return sh_i2c_read(adap, dev, 0, 0, dummy, sizeof dummy);
274 }
275
sh_i2c_set_bus_speed(struct i2c_adapter * adap,unsigned int speed)276 static unsigned int sh_i2c_set_bus_speed(struct i2c_adapter *adap,
277 unsigned int speed)
278 {
279 struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];
280
281 sh_i2c_finish(dev);
282 sh_i2c_init(adap, speed, 0);
283
284 return 0;
285 }
286
287 /*
288 * Register RCAR i2c adapters
289 */
290 U_BOOT_I2C_ADAP_COMPLETE(sh_0, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
291 sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SPEED, 0, 0)
292 #ifdef CONFIG_SYS_I2C_SH_BASE1
293 U_BOOT_I2C_ADAP_COMPLETE(sh_1, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
294 sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SPEED, 0, 1)
295 #endif
296 #ifdef CONFIG_SYS_I2C_SH_BASE2
297 U_BOOT_I2C_ADAP_COMPLETE(sh_2, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
298 sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SPEED, 0, 2)
299 #endif
300 #ifdef CONFIG_SYS_I2C_SH_BASE3
301 U_BOOT_I2C_ADAP_COMPLETE(sh_3, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
302 sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SPEED, 0, 3)
303 #endif
304 #ifdef CONFIG_SYS_I2C_SH_BASE4
305 U_BOOT_I2C_ADAP_COMPLETE(sh_4, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
306 sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SPEED, 0, 4)
307 #endif
308