1#
2# Multifunction miscellaneous devices
3#
4
5menu "Multifunction device drivers"
6
7config MISC
8	bool "Enable Driver Model for Misc drivers"
9	depends on DM
10	help
11	  Enable driver model for miscellaneous devices. This class is
12	  used only for those do not fit other more general classes. A
13	  set of generic read, write and ioctl methods may be used to
14	  access the device.
15
16config SPL_MISC
17	bool "Enable Driver Model for Misc drivers in SPL"
18	depends on SPL_DM
19	default MISC
20	help
21	  Enable driver model for miscellaneous devices. This class is
22	  used only for those do not fit other more general classes. A
23	  set of generic read, write and ioctl methods may be used to
24	  access the device.
25
26config TPL_MISC
27	bool "Enable Driver Model for Misc drivers in TPL"
28	depends on TPL_DM
29	default MISC
30	help
31	  Enable driver model for miscellaneous devices. This class is
32	  used only for those do not fit other more general classes. A
33	  set of generic read, write and ioctl methods may be used to
34	  access the device.
35
36config VPL_MISC
37	bool "Enable Driver Model for Misc drivers in VPL"
38	depends on VPL_DM
39	default MISC
40	help
41	  Enable driver model for miscellaneous devices. This class is
42	  used only for those do not fit other more general classes. A
43	  set of generic read, write and ioctl methods may be used to
44	  access the device.
45
46config NVMEM
47	bool "NVMEM support"
48	help
49	  This adds support for a common interface to different types of
50	  non-volatile memory. Consumers can use nvmem-cells properties to look
51	  up hardware configuration data such as MAC addresses and calibration
52	  settings.
53
54config SPL_NVMEM
55	bool "NVMEM support in SPL"
56	help
57	  This adds support for a common interface to different types of
58	  non-volatile memory. Consumers can use nvmem-cells properties to look
59	  up hardware configuration data such as MAC addresses and calibration
60	  settings.
61
62config ALTERA_SYSID
63	bool "Altera Sysid support"
64	depends on MISC
65	help
66	  Select this to enable a sysid for Altera devices. Please find
67	  details on the "Embedded Peripherals IP User Guide" of Altera.
68
69config ATSHA204A
70	bool "Support for Atmel ATSHA204A module"
71	select BITREVERSE
72	depends on MISC
73	help
74	   Enable support for I2C connected Atmel's ATSHA204A
75	   CryptoAuthentication module found for example on the Turris Omnia
76	   board.
77
78config GATEWORKS_SC
79	bool "Gateworks System Controller Support"
80	depends on MISC
81	help
82	  Enable access for the Gateworks System Controller used on Gateworks
83	  boards to provide a boot watchdog, power control, temperature monitor,
84	  voltage ADCs, and EEPROM.
85
86config ROCKCHIP_EFUSE
87        bool "Rockchip e-fuse support"
88	depends on MISC
89	help
90	  Enable (read-only) access for the e-fuse block found in Rockchip
91	  SoCs: accesses can either be made using byte addressing and a length
92	  or through child-nodes that are generated based on the e-fuse map
93	  retrieved from the DTS.
94
95config ROCKCHIP_OTP
96	bool "Rockchip OTP Support"
97	depends on MISC
98	help
99	  Enable (read-only) access for the one-time-programmable memory block
100	  found in Rockchip SoCs: accesses can either be made using byte
101	  addressing and a length or through child-nodes that are generated
102	  based on the e-fuse map retrieved from the DTS.
103
104config ROCKCHIP_IODOMAIN
105	bool "Rockchip IO-domain driver support"
106	depends on DM_REGULATOR && ARCH_ROCKCHIP
107	default y if ROCKCHIP_PX30
108	default y if ROCKCHIP_RK3308
109	default y if ROCKCHIP_RK3328
110	default y if ROCKCHIP_RK3399
111	default y if ROCKCHIP_RK3568
112	help
113	  Enable support for IO-domains in Rockchip SoCs. It is necessary
114	  for the IO-domain setting of the SoC to match the voltage supplied
115	  by the regulators.
116
117config SPL_ROCKCHIP_IODOMAIN
118	bool "Rockchip IO-domain driver support in SPL"
119	depends on SPL_MISC && SPL_DM_REGULATOR && ARCH_ROCKCHIP
120	help
121	  Enable support for IO-domains in Rockchip SoCs in SPL. It is necessary
122	  for the IO-domain setting of the SoC to match the voltage supplied
123	  by the regulators.
124
125config SIFIVE_OTP
126	bool "SiFive eMemory OTP driver"
127	depends on MISC
128	help
129	  Enable support for reading and writing the eMemory OTP on the
130	  SiFive SoCs.
131
132config SMSC_LPC47M
133	bool "LPC47M SMSC driver"
134
135config SMSC_SIO1007
136	bool "SIO1007 SMSC driver"
137
138config VEXPRESS_CONFIG
139	bool "Enable support for Arm Versatile Express config bus"
140	depends on MISC
141	help
142	  If you say Y here, you will get support for accessing the
143	  configuration bus on the Arm Versatile Express boards via
144	  a sysreg driver.
145
146config CBMEM_CONSOLE
147	bool "Write console output to coreboot cbmem"
148	depends on X86
149	help
150	  Enables console output to the cbmem console, which is a memory
151	  region set up by coreboot to hold a record of all console output.
152	  Enable this only if booting from coreboot.
153
154config CMD_CROS_EC
155	bool "Enable crosec command"
156	depends on CROS_EC
157	help
158	  Enable command-line access to the Chrome OS EC (Embedded
159	  Controller). This provides the 'crosec' command which has
160	  a number of sub-commands for performing EC tasks such as
161	  updating its flash, accessing a small saved context area
162	  and talking to the I2C bus behind the EC (if there is one).
163
164config CROS_EC
165	bool "Enable Chrome OS EC"
166	help
167	  Enable access to the Chrome OS EC. This is a separate
168	  microcontroller typically available on a SPI bus on Chromebooks. It
169	  provides access to the keyboard, some internal storage and may
170	  control access to the battery and main PMIC depending on the
171	  device. You can use the 'crosec' command to access it.
172
173config SPL_CROS_EC
174	bool "Enable Chrome OS EC in SPL"
175	depends on SPL_MISC
176	help
177	  Enable access to the Chrome OS EC in SPL. This is a separate
178	  microcontroller typically available on a SPI bus on Chromebooks. It
179	  provides access to the keyboard, some internal storage and may
180	  control access to the battery and main PMIC depending on the
181	  device. You can use the 'crosec' command to access it.
182
183config TPL_CROS_EC
184	bool "Enable Chrome OS EC in TPL"
185	depends on TPL_MISC
186	help
187	  Enable access to the Chrome OS EC in TPL. This is a separate
188	  microcontroller typically available on a SPI bus on Chromebooks. It
189	  provides access to the keyboard, some internal storage and may
190	  control access to the battery and main PMIC depending on the
191	  device. You can use the 'crosec' command to access it.
192
193config VPL_CROS_EC
194	bool "Enable Chrome OS EC in VPL"
195	depends on VPL_MISC
196	help
197	  Enable access to the Chrome OS EC in VPL. This is a separate
198	  microcontroller typically available on a SPI bus on Chromebooks. It
199	  provides access to the keyboard, some internal storage and may
200	  control access to the battery and main PMIC depending on the
201	  device. You can use the 'crosec' command to access it.
202
203config CROS_EC_I2C
204	bool "Enable Chrome OS EC I2C driver"
205	depends on CROS_EC
206	help
207	  Enable I2C access to the Chrome OS EC. This is used on older
208	  ARM Chromebooks such as snow and spring before the standard bus
209	  changed to SPI. The EC will accept commands across the I2C using
210	  a special message protocol, and provide responses.
211
212config CROS_EC_LPC
213	bool "Enable Chrome OS EC LPC driver"
214	depends on CROS_EC
215	help
216	  Enable I2C access to the Chrome OS EC. This is used on x86
217	  Chromebooks such as link and falco. The keyboard is provided
218	  through a legacy port interface, so on x86 machines the main
219	  function of the EC is power and thermal management.
220
221config SPL_CROS_EC_LPC
222	bool "Enable Chrome OS EC LPC driver in SPL"
223	depends on CROS_EC && SPL_MISC
224	help
225	  Enable I2C access to the Chrome OS EC. This is used on x86
226	  Chromebooks such as link and falco. The keyboard is provided
227	  through a legacy port interface, so on x86 machines the main
228	  function of the EC is power and thermal management.
229
230config TPL_CROS_EC_LPC
231	bool "Enable Chrome OS EC LPC driver in TPL"
232	depends on CROS_EC && TPL_MISC
233	help
234	  Enable I2C access to the Chrome OS EC. This is used on x86
235	  Chromebooks such as link and falco. The keyboard is provided
236	  through a legacy port interface, so on x86 machines the main
237	  function of the EC is power and thermal management.
238
239config VPL_CROS_EC_LPC
240	bool "Enable Chrome OS EC LPC driver in VPL"
241	depends on CROS_EC && VPL_MISC
242	help
243	  Enable I2C access to the Chrome OS EC. This is used on x86
244	  Chromebooks such as link and falco. The keyboard is provided
245	  through a legacy port interface, so on x86 machines the main
246	  function of the EC is power and thermal management.
247
248config CROS_EC_SANDBOX
249	bool "Enable Chrome OS EC sandbox driver"
250	depends on CROS_EC && SANDBOX
251	help
252	  Enable a sandbox emulation of the Chrome OS EC. This supports
253	  keyboard (use the -l flag to enable the LCD), verified boot context,
254	  EC flash read/write/erase support and a few other things. It is
255	  enough to perform a Chrome OS verified boot on sandbox.
256
257config SPL_CROS_EC_SANDBOX
258	bool "Enable Chrome OS EC sandbox driver in SPL"
259	depends on SPL_CROS_EC && SANDBOX
260	help
261	  Enable a sandbox emulation of the Chrome OS EC in SPL. This supports
262	  keyboard (use the -l flag to enable the LCD), verified boot context,
263	  EC flash read/write/erase support and a few other things. It is
264	  enough to perform a Chrome OS verified boot on sandbox.
265
266config TPL_CROS_EC_SANDBOX
267	bool "Enable Chrome OS EC sandbox driver in TPL"
268	depends on TPL_CROS_EC && SANDBOX
269	help
270	  Enable a sandbox emulation of the Chrome OS EC in TPL. This supports
271	  keyboard (use the -l flag to enable the LCD), verified boot context,
272	  EC flash read/write/erase support and a few other things. It is
273	  enough to perform a Chrome OS verified boot on sandbox.
274
275config VPL_CROS_EC_SANDBOX
276	bool "Enable Chrome OS EC sandbox driver in VPL"
277	depends on VPL_CROS_EC && SANDBOX
278	help
279	  Enable a sandbox emulation of the Chrome OS EC in VPL. This supports
280	  keyboard (use the -l flag to enable the LCD), verified boot context,
281	  EC flash read/write/erase support and a few other things. It is
282	  enough to perform a Chrome OS verified boot on sandbox.
283
284config CROS_EC_SPI
285	bool "Enable Chrome OS EC SPI driver"
286	depends on CROS_EC
287	help
288	  Enable SPI access to the Chrome OS EC. This is used on newer
289	  ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
290	  provides a faster and more robust interface than I2C but the bugs
291	  are less interesting.
292
293config FSL_IIM
294	bool "Enable FSL IC Identification Module (IIM) driver"
295	depends on ARCH_MX5
296
297config IRQ
298	bool "Interrupt controller"
299	help
300	  This enables support for interrupt controllers, including ITSS.
301	  Some devices have extra features, such as Apollo Lake. The
302	  device has its own uclass since there are several operations
303	  involved.
304
305config JZ4780_EFUSE
306	bool "Ingenic JZ4780 eFUSE support"
307	depends on ARCH_JZ47XX
308	help
309	  This selects support for the eFUSE on Ingenic JZ4780 SoCs.
310
311config LS2_SFP
312	bool "Layerscape Security Fuse Processor"
313	depends on FSL_LSCH2 || ARCH_LS1021A
314	depends on MISC
315	imply DM_REGULATOR
316	help
317	  This adds support for the Security Fuse Processor found on Layerscape
318	  SoCs. It contains various fuses related to secure boot, including the
319	  Super Root Key hash, One-Time-Programmable Master Key, Debug
320	  Challenge/Response values, and others. Fuses are numbered according
321	  to their four-byte offset from the start of the bank.
322
323	  If you don't need to read/program fuses, say 'n'.
324
325config MXC_OCOTP
326	bool "Enable MXC OCOTP Driver"
327	depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610
328	default y
329	help
330	  If you say Y here, you will get support for the One Time
331	  Programmable memory pages that are stored on the some
332	  Freescale i.MX processors.
333
334config MXS_OCOTP
335	bool "Enable MXS OCOTP Driver"
336	depends on ARCH_MX23 || ARCH_MX28
337	help
338	  If you say Y here, you will get support for the One Time
339	  Programmable memory pages that are stored on the
340	  Freescale i.MXS family of processors.
341
342config NPCM_HOST
343	bool "Enable support espi or LPC for Host"
344	depends on REGMAP && SYSCON
345	help
346	  Enable NPCM BMC espi or LPC support for Host reading and writing.
347
348config SPL_MXC_OCOTP
349	bool "Enable MXC OCOTP driver in SPL"
350	depends on SPL_DRIVERS_MISC && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610)
351	default y
352	help
353	  If you say Y here, you will get support for the One Time
354	  Programmable memory pages, that are stored on some
355	  Freescale i.MX processors, in SPL.
356
357config NPCM_OTP
358	bool "Nnvoton NPCM BMC On-Chip OTP Memory Support"
359	depends on (ARM && ARCH_NPCM)
360	help
361	  Support NPCM BMC OTP memory (fuse).
362	  To compile this driver as a module, choose M here: the module
363	  will be called npcm_otp.
364
365config IMX_ELE
366	bool "Enable i.MX EdgeLock Enclave MU driver and API"
367	depends on MISC && (ARCH_IMX9 || ARCH_IMX8ULP)
368	help
369	  If you say Y here to enable Message Unit driver to work with
370	  Sentinel core on some NXP i.MX processors.
371
372config NUVOTON_NCT6102D
373	bool "Enable Nuvoton NCT6102D Super I/O driver"
374	help
375	  If you say Y here, you will get support for the Nuvoton
376	  NCT6102D Super I/O driver. This can be used to enable or
377	  disable the legacy UART, the watchdog or other devices
378	  in the Nuvoton Super IO chips on X86 platforms.
379
380config P2SB
381	bool "Intel Primary to Sideband Bridge"
382	depends on X86 || SANDBOX
383	help
384	  This enables support for the Intel Primary to Sideband Bridge,
385	  abbreviated to P2SB. The P2SB is used to access various peripherals
386	  such as eSPI, GPIO, through memory-mapped I/O in a large chunk of PCI
387	  space. The space is segmented into different channels and peripherals
388	  are accessed by device-specific means within those channels. Devices
389	  should be added in the device tree as subnodes of the P2SB. A
390	  Peripheral Channel Register? (PCR) API is provided to access those
391	  devices - see pcr_readl(), etc.
392
393config SPL_P2SB
394	bool "Intel Primary to Sideband Bridge in SPL"
395	depends on SPL_MISC && (X86 || SANDBOX)
396	help
397	  The Primary to Sideband Bridge is used to access various peripherals
398	  through memory-mapped I/O in a large chunk of PCI space. The space is
399	  segmented into different channels and peripherals are accessed by
400	  device-specific means within those channels. Devices should be added
401	  in the device tree as subnodes of the p2sb.
402
403config TPL_P2SB
404	bool "Intel Primary to Sideband Bridge in TPL"
405	depends on TPL_MISC && (X86 || SANDBOX)
406	help
407	  The Primary to Sideband Bridge is used to access various peripherals
408	  through memory-mapped I/O in a large chunk of PCI space. The space is
409	  segmented into different channels and peripherals are accessed by
410	  device-specific means within those channels. Devices should be added
411	  in the device tree as subnodes of the p2sb.
412
413config PWRSEQ
414	bool "Enable power-sequencing drivers"
415	depends on DM
416	help
417	  Power-sequencing drivers provide support for controlling power for
418	  devices. They are typically referenced by a phandle from another
419	  device. When the device is started up, its power sequence can be
420	  initiated.
421
422config SPL_PWRSEQ
423	bool "Enable power-sequencing drivers for SPL"
424	depends on SPL_MISC && PWRSEQ
425	help
426	  Power-sequencing drivers provide support for controlling power for
427	  devices. They are typically referenced by a phandle from another
428	  device. When the device is started up, its power sequence can be
429	  initiated.
430
431config STM32MP_FUSE
432	bool "Enable STM32MP fuse wrapper providing the fuse API"
433	depends on ARCH_STM32MP && MISC
434	default y if CMD_FUSE
435	help
436	  If you say Y here, you will get support for the fuse API (OTP)
437	  for STM32MP architecture.
438	  This API is needed for CMD_FUSE.
439
440config K3_FUSE
441	bool "Enable TI K3 fuse wrapper providing the fuse API"
442	depends on MISC && CMD_FUSE && CMD_FUSE_WRITEBUFF
443	help
444	  If you say Y here, you will get support for the fuse API (OTP)
445	  for TI K3 architecture.
446
447config STM32_RCC
448	bool "Enable RCC driver for the STM32 SoC's family"
449	depends on (ARCH_STM32 || ARCH_STM32MP) && MISC
450	help
451	  Enable the STM32 RCC driver. The RCC block (Reset and Clock Control
452	  block) is responsible of the management of the clock and reset
453	  generation.
454	  This driver is similar to an MFD driver in the Linux kernel.
455
456config TEGRA_CAR
457	bool "Enable support for the Tegra CAR driver"
458	depends on TEGRA_NO_BPMP
459	help
460	  The Tegra CAR (Clock and Reset Controller) is a HW module that
461	  controls almost all clocks and resets in a Tegra SoC.
462
463config TEGRA186_BPMP
464	bool "Enable support for the Tegra186 BPMP driver"
465	depends on TEGRA186
466	help
467	  The Tegra BPMP (Boot and Power Management Processor) is a separate
468	  auxiliary CPU embedded into Tegra to perform power management work,
469	  and controls related features such as clocks, resets, power domains,
470	  PMIC I2C bus, etc. This driver provides the core low-level
471	  communication path by which feature-specific drivers (such as clock)
472	  can make requests to the BPMP. This driver is similar to an MFD
473	  driver in the Linux kernel.
474
475config TEST_DRV
476	bool "Enable support for test drivers"
477	default y if SANDBOX
478	help
479	  This enables drivers and uclasses that provides a way of testing the
480	  operations of memory allocation and driver/uclass methods in driver
481	  model. This should only be enabled for testing as it is not useful for
482	  anything else.
483
484config TURRIS_OMNIA_MCU
485	bool "Enable Turris Omnia MCU driver"
486	depends on DM_I2C
487	depends on DM_GPIO
488	depends on DM_RNG
489	depends on SYSRESET
490	default y if TARGET_TURRIS_OMNIA
491	help
492	  This enables support for Turris Omnia MCU connected GPIOs and
493	  board power off.
494
495config USB_HUB_USB251XB
496	tristate "USB251XB Hub Controller Configuration Driver"
497	depends on I2C
498	help
499	  This option enables support for configuration via SMBus of the
500	  Microchip USB251x/xBi USB 2.0 Hub Controller series. Configuration
501	  parameters may be set in devicetree or platform data.
502	  Say Y or M here if you need to configure such a device via SMBus.
503
504config TWL4030_LED
505	bool "Enable TWL4030 LED controller"
506	help
507	  Enable this to add support for the TWL4030 LED controller.
508
509config WINBOND_W83627
510	bool "Enable Winbond Super I/O driver"
511	help
512	  If you say Y here, you will get support for the Winbond
513	  W83627 Super I/O driver. This can be used to enable the
514	  legacy UART or other devices in the Winbond Super IO chips
515	  on X86 platforms.
516
517config QFW
518	bool
519	help
520	  Hidden option to enable QEMU fw_cfg interface and uclass. This will
521	  be selected by either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
522
523config QFW_ACPI
524	bool
525	default y
526	depends on QFW && GENERATE_ACPI_TABLE && !SANDBOX
527	help
528	  Hidden option to read ACPI tables from QEMU.
529
530config QFW_PIO
531	bool
532	depends on QFW
533	help
534	  Hidden option to enable PIO QEMU fw_cfg interface. This will be
535	  selected by the appropriate QEMU board.
536
537config QFW_MMIO
538	bool
539	depends on QFW
540	help
541	  Hidden option to enable MMIO QEMU fw_cfg interface. This will be
542	  selected by the appropriate QEMU board.
543
544config QFW_SMBIOS
545	bool
546	default y
547	depends on QFW && SMBIOS && !SANDBOX && !SYSINFO_SMBIOS
548	select BLOBLIST
549	help
550	  Hidden option to read SMBIOS tables from QEMU.
551
552config I2C_EEPROM
553	bool "Enable driver for generic I2C-attached EEPROMs"
554	depends on MISC
555	help
556	  Enable a generic driver for EEPROMs attached via I2C.
557
558
559config SPL_I2C_EEPROM
560	bool "Enable driver for generic I2C-attached EEPROMs for SPL"
561	depends on SPL_MISC
562	help
563	  This option is an SPL-variant of the I2C_EEPROM option.
564	  See the help of I2C_EEPROM for details.
565
566config SYS_I2C_EEPROM_ADDR
567	hex "Chip address of the EEPROM device"
568	depends on ID_EEPROM || I2C_EEPROM || SPL_I2C_EEPROM || CMD_EEPROM || ENV_IS_IN_EEPROM
569	default 0x0
570
571if I2C_EEPROM
572
573config SYS_I2C_EEPROM_ADDR_OVERFLOW
574	hex "EEPROM Address Overflow"
575	default 0x0
576	help
577	  EEPROM chips that implement "address overflow" are ones
578	  like Catalyst 24WC04/08/16 which has 9/10/11 bits of
579	  address and the extra bits end up in the "chip address" bit
580	  slots. This makes a 24WC08 (1Kbyte) chip look like four 256
581	  byte chips.
582
583endif
584
585config GDSYS_RXAUI_CTRL
586	bool "Enable gdsys RXAUI control driver"
587	depends on MISC
588	help
589	  Support gdsys FPGA's RXAUI control.
590
591config GDSYS_IOEP
592	bool "Enable gdsys IOEP driver"
593	depends on MISC
594	help
595	  Support gdsys FPGA's IO endpoint driver.
596
597config MPC83XX_SERDES
598	bool "Enable MPC83xx serdes driver"
599	depends on MISC
600	help
601	  Support for serdes found on MPC83xx SoCs.
602
603config FS_LOADER
604	bool "Enable loader driver for file system"
605	help
606	  This is file system generic loader which can be used to load
607	  the file image from the storage into target such as memory.
608
609	  The consumer driver would then use this loader to program whatever,
610	  ie. the FPGA device.
611
612config SPL_FS_LOADER
613	bool "Enable loader driver for file system in SPL"
614	depends on SPL
615	help
616	  This is file system generic loader which can be used to load
617	  the file image from the storage into target such as memory.
618
619	  The consumer driver would then use this loader to program whatever,
620	  ie. the FPGA device.
621
622config GDSYS_SOC
623	bool "Enable gdsys SOC driver"
624	depends on MISC
625	help
626	  Support for gdsys IHS SOC, a simple bus associated with each gdsys
627	  IHS (Integrated Hardware Systems) FPGA, which holds all devices whose
628	  register maps are contained within the FPGA's register map.
629
630config IHS_FPGA
631	bool "Enable IHS FPGA driver"
632	depends on MISC && (GDSYS_LEGACY_DRIVERS || SYS_FPGA_FLAVOR_GAZERBEAM)
633	help
634	  Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on
635	  gdsys devices, which supply the majority of the functionality offered
636	  by the devices. This driver supports both CON and CPU variants of the
637	  devices, depending on the device tree entry.
638config ESM_K3
639	bool "Enable K3 ESM driver"
640	depends on ARCH_K3
641	help
642	  Support ESM (Error Signaling Module) on TI K3 SoCs.
643
644config K3_BIST
645	bool "Enable K3 BIST driver"
646	depends on ARCH_K3
647	help
648	  Support BIST (Built-In Self Test) module on TI K3 SoCs. This driver
649	  supports running both PBIST (Memory BIST) and LBIST (Logic BIST) on
650	  a region or IP in the SoC.
651
652config MICROCHIP_FLEXCOM
653	bool "Enable Microchip Flexcom driver"
654	depends on MISC
655	help
656	  The Atmel Flexcom is just a wrapper which embeds a SPI controller,
657	  an I2C controller and an USART.
658	  Only one function can be used at a time and is chosen at boot time
659	  according to the device tree.
660
661config MPFS_SYSCONTROLLER
662	bool "Enable Microchip PolarFire SoC (MPFS) System Services support"
663	depends on MISC
664	depends on MPFS_MBOX
665	help
666	  This driver adds support for the PolarFire SoC (MPFS) system controller.
667
668	  If unsure, say N.
669
670config K3_AVS0
671	depends on ARCH_K3 && SPL_DM_REGULATOR
672	bool "AVS class 0 support for K3 devices"
673	help
674	  K3 devices have the optimized voltage values for the main voltage
675	  domains stored in efuse within the VTM IP. This driver reads the
676	  optimized voltage from the efuse, so that it can be programmed
677	  to the PMIC on board.
678
679config ESM_PMIC
680	bool "Enable PMIC ESM driver"
681	depends on DM_PMIC
682	help
683	  Support ESM (Error Signal Monitor) on PMIC devices. ESM is used
684	  typically to reboot the board in error condition.
685
686config FSL_IFC
687	bool
688
689config SL28CPLD
690	bool "Enable Kontron sl28cpld multi-function driver"
691	depends on DM_I2C
692	help
693	  Support for the Kontron sl28cpld management controller. This is
694	  the base driver which provides common access methods for the
695	  sub-drivers.
696
697config SPL_SOCFPGA_DT_REG
698	bool "Enable register setting from device tree in SPL"
699	depends on SPL
700	help
701	  Enable register setting from device tree. This also
702	  provides user a clean interface and all register settings are
703	  centralized in one place, device tree.
704endmenu
705