1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Static Data for Texas Instruments' BIST logic for J784S4 4 * 5 * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ 6 * 7 */ 8 9 /* Device IDs of IPs that can be tested under BIST */ 10 #define TISCI_DEV_MCU_R5FSS2_CORE0 343 11 #define TISCI_DEV_MCU_R5FSS2_CORE1 344 12 #define TISCI_DEV_RTI32 365 13 #define TISCI_DEV_RTI33 366 14 15 /* WKUP CTRL MMR Registers */ 16 #define WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT 0x0000C2C0 17 #define WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT_POST_MCU_PBIST_DONE_SHIFT 0x00000008 18 #define WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT_POST_MCU_LBIST_DONE_SHIFT 0x00000001 19 #define WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT_POST_MCU_PBIST_TIMEOUT_SHIFT 0x00000009 20 #define WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT_POST_MCU_LBIST_TIMEOUT_SHIFT 0x00000005 21 #define WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT_POST_MCU_PBIST_FAIL_MASK 0x00008000 22 23 /* MCU CTRL MMR Register */ 24 #define MCU_CTRL_MMR0_CFG0_BASE 0x40f00000 25 #define MCU_CTRL_MMR_CFG0_MCU_LBIST_CTRL 0x0000c000 26 #define MCU_CTRL_MMR_CFG0_MCU_LBIST_SIG 0x0000c280 27 #define MCU_LBIST_BASE (MCU_CTRL_MMR0_CFG0_BASE + \ 28 MCU_CTRL_MMR_CFG0_MCU_LBIST_CTRL) 29 30 /* Properties of PBIST instances in: PBIST14 */ 31 #define PBIST14_DEV_ID 234 32 #define PBIST14_NUM_TEST_VECTORS 0x1 33 #define PBIST14_ALGO_BITMAP_0 0x00000003 34 #define PBIST14_MEM_BITMAP_0 0x000CCCCC 35 #define PBIST14_FAIL_INSERTION_TEST_VECTOR_CA0 0x00000000 36 #define PBIST14_FAIL_INSERTION_TEST_VECTOR_CA1 0x000001FF 37 #define PBIST14_FAIL_INSERTION_TEST_VECTOR_CA2 0x000001FF 38 #define PBIST14_FAIL_INSERTION_TEST_VECTOR_CA3 0x00000000 39 #define PBIST14_FAIL_INSERTION_TEST_VECTOR_CL0 0x0000007F 40 #define PBIST14_FAIL_INSERTION_TEST_VECTOR_CL1 0x00000003 41 #define PBIST14_FAIL_INSERTION_TEST_VECTOR_CL2 0x00000008 42 #define PBIST14_FAIL_INSERTION_TEST_VECTOR_CL3 0x000001FF 43 #define PBIST14_FAIL_INSERTION_TEST_VECTOR_CMS 0x00000000 44 #define PBIST14_FAIL_INSERTION_TEST_VECTOR_CSR 0x20000000 45 #define PBIST14_FAIL_INSERTION_TEST_VECTOR_I0 0x00000001 46 #define PBIST14_FAIL_INSERTION_TEST_VECTOR_I1 0x00000004 47 #define PBIST14_FAIL_INSERTION_TEST_VECTOR_I2 0x00000008 48 #define PBIST14_FAIL_INSERTION_TEST_VECTOR_I3 0x00000000 49 #define PBIST14_FAIL_INSERTION_TEST_VECTOR_RAMT 0x011D2528 50 51 static struct pbist_inst_info pbist14_inst_info = { 52 /* Main Pulsar 2 Instance 1 or MAIN_R52_x */ 53 .num_pbist_runs = 1, 54 .intr_num = PBIST14_DFT_PBIST_CPU_0_INTR_NUM, 55 .dev_id = TISCI_DEV_PBIST14, 56 .cut = { 57 { 58 .dev_id = TISCI_DEV_R5FSS2_CORE0, 59 .proc_id = PROC_ID_MCU_R5FSS2_CORE0, 60 }, 61 { 62 .dev_id = TISCI_DEV_R5FSS2_CORE1, 63 .proc_id = PROC_ID_MCU_R5FSS2_CORE1, 64 } 65 }, 66 .pbist_config_run = { 67 { 68 .override = 0, 69 .algorithms_bit_map = PBIST14_ALGO_BITMAP_0, 70 .memory_groups_bit_map = PBIST14_MEM_BITMAP_0, 71 .scramble_value_lo = 0x76543210, 72 .scramble_value_hi = 0xFEDCBA98, 73 }, 74 { 75 .override = 0, 76 .algorithms_bit_map = 0, 77 .memory_groups_bit_map = 0, 78 .scramble_value_lo = 0, 79 .scramble_value_hi = 0, 80 }, 81 }, 82 .pbist_neg_config_run = { 83 .CA0 = PBIST14_FAIL_INSERTION_TEST_VECTOR_CA0, 84 .CA1 = PBIST14_FAIL_INSERTION_TEST_VECTOR_CA1, 85 .CA2 = PBIST14_FAIL_INSERTION_TEST_VECTOR_CA2, 86 .CA3 = PBIST14_FAIL_INSERTION_TEST_VECTOR_CA3, 87 .CL0 = PBIST14_FAIL_INSERTION_TEST_VECTOR_CL0, 88 .CL1 = PBIST14_FAIL_INSERTION_TEST_VECTOR_CL1, 89 .CL2 = PBIST14_FAIL_INSERTION_TEST_VECTOR_CL2, 90 .CL3 = PBIST14_FAIL_INSERTION_TEST_VECTOR_CL3, 91 .CMS = PBIST14_FAIL_INSERTION_TEST_VECTOR_CMS, 92 .CSR = PBIST14_FAIL_INSERTION_TEST_VECTOR_CSR, 93 .I0 = PBIST14_FAIL_INSERTION_TEST_VECTOR_I0, 94 .I1 = PBIST14_FAIL_INSERTION_TEST_VECTOR_I1, 95 .I2 = PBIST14_FAIL_INSERTION_TEST_VECTOR_I2, 96 .I3 = PBIST14_FAIL_INSERTION_TEST_VECTOR_I3, 97 .RAMT = PBIST14_FAIL_INSERTION_TEST_VECTOR_RAMT 98 }, 99 .num_pbist_rom_test_runs = 1, 100 .pbist_rom_test_config_run = { 101 { 102 .D = 0xF412605Eu, 103 .E = 0xF412605Eu, 104 .CA2 = 0x7FFFu, 105 .CL0 = 0x3FFu, 106 .CA3 = 0x0u, 107 .I0 = 0x1u, 108 .CL1 = 0x1Fu, 109 .I3 = 0x0u, 110 .I2 = 0xEu, 111 .CL2 = 0xEu, 112 .CA1 = 0x7FFFu, 113 .CA0 = 0x0u, 114 .CL3 = 0x7FFFu, 115 .I1 = 0x20u, 116 .RAMT = 0x08002020u, 117 .CSR = 0x00000001u, 118 .CMS = 0x01u 119 }, 120 { 121 .D = 0x0u, 122 .E = 0x0u, 123 .CA2 = 0x0u, 124 .CL0 = 0x0u, 125 .CA3 = 0x0u, 126 .I0 = 0x0u, 127 .CL1 = 0x0u, 128 .I3 = 0x0u, 129 .I2 = 0x0u, 130 .CL2 = 0x0u, 131 .CA1 = 0x0u, 132 .CA0 = 0x0u, 133 .CL3 = 0x0u, 134 .I1 = 0x0u, 135 .RAMT = 0x0u, 136 .CSR = 0x0u, 137 .CMS = 0x0u 138 }, 139 { 140 .D = 0x0u, 141 .E = 0x0u, 142 .CA2 = 0x0u, 143 .CL0 = 0x0u, 144 .CA3 = 0x0u, 145 .I0 = 0x0u, 146 .CL1 = 0x0u, 147 .I3 = 0x0u, 148 .I2 = 0x0u, 149 .CL2 = 0x0u, 150 .CA1 = 0x0u, 151 .CA0 = 0x0u, 152 .CL3 = 0x0u, 153 .I1 = 0x0u, 154 .RAMT = 0x0u, 155 .CSR = 0x0u, 156 .CMS = 0x0u 157 }, 158 { 159 .D = 0x0u, 160 .E = 0x0u, 161 .CA2 = 0x0u, 162 .CL0 = 0x0u, 163 .CA3 = 0x0u, 164 .I0 = 0x0u, 165 .CL1 = 0x0u, 166 .I3 = 0x0u, 167 .I2 = 0x0u, 168 .CL2 = 0x0u, 169 .CA1 = 0x0u, 170 .CA0 = 0x0u, 171 .CL3 = 0x0u, 172 .I1 = 0x0u, 173 .RAMT = 0x0u, 174 .CSR = 0x0u, 175 .CMS = 0x0u 176 }, 177 { 178 .D = 0x0u, 179 .E = 0x0u, 180 .CA2 = 0x0u, 181 .CL0 = 0x0u, 182 .CA3 = 0x0u, 183 .I0 = 0x0u, 184 .CL1 = 0x0u, 185 .I3 = 0x0u, 186 .I2 = 0x0u, 187 .CL2 = 0x0u, 188 .CA1 = 0x0u, 189 .CA0 = 0x0u, 190 .CL3 = 0x0u, 191 .I1 = 0x0u, 192 .RAMT = 0x0u, 193 .CSR = 0x0u, 194 .CMS = 0x0u 195 }, 196 { 197 .D = 0x0u, 198 .E = 0x0u, 199 .CA2 = 0x0u, 200 .CL0 = 0x0u, 201 .CA3 = 0x0u, 202 .I0 = 0x0u, 203 .CL1 = 0x0u, 204 .I3 = 0x0u, 205 .I2 = 0x0u, 206 .CL2 = 0x0u, 207 .CA1 = 0x0u, 208 .CA0 = 0x0u, 209 .CL3 = 0x0u, 210 .I1 = 0x0u, 211 .RAMT = 0x0u, 212 .CSR = 0x0u, 213 .CMS = 0x0u 214 }, 215 { 216 .D = 0x0u, 217 .E = 0x0u, 218 .CA2 = 0x0u, 219 .CL0 = 0x0u, 220 .CA3 = 0x0u, 221 .I0 = 0x0u, 222 .CL1 = 0x0u, 223 .I3 = 0x0u, 224 .I2 = 0x0u, 225 .CL2 = 0x0u, 226 .CA1 = 0x0u, 227 .CA0 = 0x0u, 228 .CL3 = 0x0u, 229 .I1 = 0x0u, 230 .RAMT = 0x0u, 231 .CSR = 0x0u, 232 .CMS = 0x0u 233 }, 234 { 235 .D = 0x0u, 236 .E = 0x0u, 237 .CA2 = 0x0u, 238 .CL0 = 0x0u, 239 .CA3 = 0x0u, 240 .I0 = 0x0u, 241 .CL1 = 0x0u, 242 .I3 = 0x0u, 243 .I2 = 0x0u, 244 .CL2 = 0x0u, 245 .CA1 = 0x0u, 246 .CA0 = 0x0u, 247 .CL3 = 0x0u, 248 .I1 = 0x0u, 249 .RAMT = 0x0u, 250 .CSR = 0x0u, 251 .CMS = 0x0u 252 }, 253 { 254 .D = 0x0u, 255 .E = 0x0u, 256 .CA2 = 0x0u, 257 .CL0 = 0x0u, 258 .CA3 = 0x0u, 259 .I0 = 0x0u, 260 .CL1 = 0x0u, 261 .I3 = 0x0u, 262 .I2 = 0x0u, 263 .CL2 = 0x0u, 264 .CA1 = 0x0u, 265 .CA0 = 0x0u, 266 .CL3 = 0x0u, 267 .I1 = 0x0u, 268 .RAMT = 0x0u, 269 .CSR = 0x0u, 270 .CMS = 0x0u 271 }, 272 { 273 .D = 0x0u, 274 .E = 0x0u, 275 .CA2 = 0x0u, 276 .CL0 = 0x0u, 277 .CA3 = 0x0u, 278 .I0 = 0x0u, 279 .CL1 = 0x0u, 280 .I3 = 0x0u, 281 .I2 = 0x0u, 282 .CL2 = 0x0u, 283 .CA1 = 0x0u, 284 .CA0 = 0x0u, 285 .CL3 = 0x0u, 286 .I1 = 0x0u, 287 .RAMT = 0x0u, 288 .CSR = 0x0u, 289 .CMS = 0x0u 290 }, 291 { 292 .D = 0x0u, 293 .E = 0x0u, 294 .CA2 = 0x0u, 295 .CL0 = 0x0u, 296 .CA3 = 0x0u, 297 .I0 = 0x0u, 298 .CL1 = 0x0u, 299 .I3 = 0x0u, 300 .I2 = 0x0u, 301 .CL2 = 0x0u, 302 .CA1 = 0x0u, 303 .CA0 = 0x0u, 304 .CL3 = 0x0u, 305 .I1 = 0x0u, 306 .RAMT = 0x0u, 307 .CSR = 0x0u, 308 .CMS = 0x0u 309 }, 310 { 311 .D = 0x0u, 312 .E = 0x0u, 313 .CA2 = 0x0u, 314 .CL0 = 0x0u, 315 .CA3 = 0x0u, 316 .I0 = 0x0u, 317 .CL1 = 0x0u, 318 .I3 = 0x0u, 319 .I2 = 0x0u, 320 .CL2 = 0x0u, 321 .CA1 = 0x0u, 322 .CA0 = 0x0u, 323 .CL3 = 0x0u, 324 .I1 = 0x0u, 325 .RAMT = 0x0u, 326 .CSR = 0x0u, 327 .CMS = 0x0u 328 }, 329 { 330 .D = 0x0u, 331 .E = 0x0u, 332 .CA2 = 0x0u, 333 .CL0 = 0x0u, 334 .CA3 = 0x0u, 335 .I0 = 0x0u, 336 .CL1 = 0x0u, 337 .I3 = 0x0u, 338 .I2 = 0x0u, 339 .CL2 = 0x0u, 340 .CA1 = 0x0u, 341 .CA0 = 0x0u, 342 .CL3 = 0x0u, 343 .I1 = 0x0u, 344 .RAMT = 0x0u, 345 .CSR = 0x0u, 346 .CMS = 0x0u 347 }, 348 }, 349 }; 350 351 static struct lbist_inst_info lbist_inst_info_main_r5f2_x = { 352 /* Main Pulsar 2 Instance 1 or MAIN_R52_x */ 353 .lbist_signature = (u32 *)(MAIN_R5F2_LBIST_SIG), 354 .intr_num = MCU_R5FSS0_CORE0_INTR_LBIST_BIST_DONE_0, 355 .expected_misr = MAIN_R5_MISR_EXP_VAL, 356 .lbist_conf = { 357 .dc_def = LBIST_DC_DEF, 358 .divide_ratio = LBIST_DIVIDE_RATIO, 359 .static_pc_def = LBIST_MAIN_R5_STATIC_PC_DEF, 360 .set_pc_def = LBIST_SET_PC_DEF, 361 .reset_pc_def = LBIST_RESET_PC_DEF, 362 .scan_pc_def = LBIST_SCAN_PC_DEF, 363 .prpg_def_l = LBIST_PRPG_DEF_L, 364 .prpg_def_u = LBIST_PRPG_DEF_U, 365 }, 366 .cut = { 367 .dev_id = TISCI_DEV_R5FSS2_CORE0, 368 .proc_id = PROC_ID_MCU_R5FSS2_CORE0, 369 }, 370 }; 371