1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
4 */
5
6 #include <asm/io.h>
7 #include <errno.h>
8 #include <smsc_sio1007.h>
9
sio1007_read(int port,int reg)10 static inline u8 sio1007_read(int port, int reg)
11 {
12 outb(reg, port);
13
14 return inb(port + 1);
15 }
16
sio1007_write(int port,int reg,int val)17 static inline void sio1007_write(int port, int reg, int val)
18 {
19 outb(reg, port);
20 outb(val, port + 1);
21 }
22
sio1007_clrsetbits(int port,int reg,u8 clr,u8 set)23 static inline void sio1007_clrsetbits(int port, int reg, u8 clr, u8 set)
24 {
25 sio1007_write(port, reg, (sio1007_read(port, reg) & ~clr) | set);
26 }
27
sio1007_enable_serial(int port,int num,int iobase,int irq)28 void sio1007_enable_serial(int port, int num, int iobase, int irq)
29 {
30 if (num < 0 || num > SIO1007_UART_NUM)
31 return;
32
33 /* enter configuration state */
34 outb(0x55, port);
35
36 /* power on serial port and set up its i/o base & irq */
37 if (!num) {
38 sio1007_clrsetbits(port, DEV_POWER_CTRL, 0, UART1_POWER_ON);
39 sio1007_clrsetbits(port, UART1_IOBASE, 0xfe, iobase >> 2);
40 sio1007_clrsetbits(port, UART_IRQ, 0xf0, irq << 4);
41 } else {
42 sio1007_clrsetbits(port, DEV_POWER_CTRL, 0, UART2_POWER_ON);
43 sio1007_clrsetbits(port, UART2_IOBASE, 0xfe, iobase >> 2);
44 sio1007_clrsetbits(port, UART_IRQ, 0x0f, irq);
45 }
46
47 /* exit configuration state */
48 outb(0xaa, port);
49 }
50
sio1007_enable_runtime(int port,int iobase)51 void sio1007_enable_runtime(int port, int iobase)
52 {
53 /* enter configuration state */
54 outb(0x55, port);
55
56 /* set i/o base for the runtime register block */
57 sio1007_clrsetbits(port, RTR_IOBASE_LOW, 0, iobase >> 4);
58 sio1007_clrsetbits(port, RTR_IOBASE_HIGH, 0, iobase >> 12);
59 /* turn on address decoding for this block */
60 sio1007_clrsetbits(port, DEV_ACTIVATE, 0, RTR_EN);
61
62 /* exit configuration state */
63 outb(0xaa, port);
64 }
65
sio1007_gpio_config(int port,int gpio,int dir,int pol,int type)66 void sio1007_gpio_config(int port, int gpio, int dir, int pol, int type)
67 {
68 int reg = GPIO0_DIR;
69
70 if (gpio < 0 || gpio > SIO1007_GPIO_NUM)
71 return;
72 if (gpio >= GPIO_NUM_PER_GROUP) {
73 reg = GPIO1_DIR;
74 gpio -= GPIO_NUM_PER_GROUP;
75 }
76
77 /* enter configuration state */
78 outb(0x55, port);
79
80 /* set gpio pin direction, polority and type */
81 sio1007_clrsetbits(port, reg, 1 << gpio, dir << gpio);
82 sio1007_clrsetbits(port, reg + 1, 1 << gpio, pol << gpio);
83 sio1007_clrsetbits(port, reg + 2, 1 << gpio, type << gpio);
84
85 /* exit configuration state */
86 outb(0xaa, port);
87 }
88
sio1007_gpio_get_value(int port,int gpio)89 int sio1007_gpio_get_value(int port, int gpio)
90 {
91 int reg = GPIO0_DATA;
92 int val;
93
94 if (gpio < 0 || gpio > SIO1007_GPIO_NUM)
95 return -EINVAL;
96 if (gpio >= GPIO_NUM_PER_GROUP) {
97 reg = GPIO1_DATA;
98 gpio -= GPIO_NUM_PER_GROUP;
99 }
100
101 val = inb(port + reg);
102 if (val & (1 << gpio))
103 return 1;
104 else
105 return 0;
106 }
107
sio1007_gpio_set_value(int port,int gpio,int val)108 void sio1007_gpio_set_value(int port, int gpio, int val)
109 {
110 int reg = GPIO0_DATA;
111 u8 data;
112
113 if (gpio < 0 || gpio > SIO1007_GPIO_NUM)
114 return;
115 if (gpio >= GPIO_NUM_PER_GROUP) {
116 reg = GPIO1_DATA;
117 gpio -= GPIO_NUM_PER_GROUP;
118 }
119
120 data = inb(port + reg);
121 data &= ~(1 << gpio);
122 data |= (val << gpio);
123 outb(data, port + reg);
124 }
125